SH3100 Datasheet, PDF (28/80 Pages) Semtech Corporation – Supervisory IC with I2C Interface and PWM

SH3100
POWER MANAGEMENT
Register Descriptions (continued)
Address(hex): 18
Register Name ADCConfig
Bit 7
Bit 6
Bit 5
Initiate ADC
Conversion
Bit No.
Comparator
polarity
Description
[7]
Initiate ADC Conversion
[6]
[5:3]
Comparator Polarity
DeviceMode
THIS REGISTER IS FUSE
INITIALIZED
[2:1]
DACClkPostScaler
[0]
DAC Enable
Description
Bit 4
(R/W) Configures ADC, DAC and Default Value: 0000 0100
comparator configuration, as ^{Reset Event: P, W}
well as setting the overall device
mode
Bit 3
Bit 2
Bit 1
Bit 0
Device mode
Bit Value
1
0
1
000
001
011
100
101
00
01
10
11
0
1
DAC Clock post-scaler
DAC Enable
Value Description
Setting this bit initiates an ADC conversion
The conversion is completed within 1500 cycles of the internal
DAC clock, the rate of which is determined by the
DACClkPostScaler in this register, and the rate of the HFDCO.
ADC conversion completion is signaled by the ADCDone flag in
the InterruptStatus register
General-purpose comparator output is used directly
General-purpose comparator output is inverted
Normal mode – PWM pin can be controlled by setting the
PWMDutyCycle
Switched boost regulator mode – PWM pin controls an external
inductor/capacitor network
Switched buck regulator mode
LDO Mode – PWM pin is driven by internal LDO
Fan control mode – PWM pin is controlled as described in the
PWM section
Note that this register may not be changed if the
App-specificFuseWP bit in the WriteProtects register is set
DACClk is 32.768 kHz (ADC Conversion in 45 ms)
DACClk is HFDCO/8 (ADC Conversion in 11264 cycles of HFDCO
period)
DACClk is HFDCO/16 (ADC Conversion in 22528 cycles of
HFDCO period)
DACClk is HFDCO/32 (ADC conversion in 45056 cycles of
HFDCO period)
General-purpose DAC & comparator are powered down
General-purpose DAC & comparator are enabled
© 2006 Semtech Corp.
28
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