SH3100 Datasheet, PDF (70/80 Pages) Semtech Corporation – Supervisory IC with I2C Interface and PWM

SH3100
POWER MANAGEMENT
Functional Descriptions (continued)
Low Dropout Linear Regulator (LDO)
The LDO function provides low-dropout linear regulation
from VDD to the PWM pin. All other PWM pin related func-
tions are disabled in this mode.
The LDO is intended as a low-power support feature for
simple low-cost applications. It has good VDD high fre-
quency noise rejection so can be used to clean up a VDD
supply.
The output voltage on PWM is determined by the DACLev-
el setting as per the previous table. The voltage on PWM
is divided by three and regulated to the same voltage as
the DAC8.
There is also a feature to allow the DAC8 to be used for
an ADC conversion while the LDO is active. To do this, the
MaintainRegulatorOp bit in the Config register should be
set prior to initiating a conversion. This disconnects the
LDO regulator input from the DAC8 and holds the refer-
ence level on a capacitor while the DAC8 is used for the
conversion. When the conversion is complete, the DAC8 is
reset to the correct level and reconnected to the LDO. Due
to internal leakage, it is recommended that the maximum
disconnect period is kept to 1ms or less.
Note: Only DAC levels of 1V and above are valid in this mode.
These LDO specifications assume a 1μF ceramic load ca-
pacitor on PWM:
Parameter
Symbol
Min
VDD input voltage
VDD
3.1
PWM output voltage
VLDO
3
No load standby current
Idd
Line regulation
REGlin
Load regulation
REGload
VDD noise rejection (100 kHz square wave PSRR
30
on VDD, >250 mV headroom)
Max load current (VLDO = 3 V)
Iload1
10
Max load current (VLDO = 4.5 V)
Iload2
15
Dropout at 10 mA load (50 mV headroom) Vdo
PWM Drift (DAC8 disconnected)
Vdrift
10 Hz to 100 kHz RMS output noise
Ntot
Max
Units
5.5
V
4.5
V
250
μA
10
mV/V
2
mV/mA
dB
mA
mA
200
mV
300
mV/ms
100
μV
© 2006 Semtech Corp.
70
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