SH3100 Datasheet, PDF (62/80 Pages) Semtech Corporation – Supervisory IC with I2C Interface and PWM

SH3100
POWER MANAGEMENT
Functional Descriptions (continued)
Interrupt Operation
There are five sources of interrupt:
• PIT interrupt – generates an interrupt every time the
PIT expires
• RTC alarm interrupt
• The interrupt can be programmed to toggle (PIT nly),
and can be used in this way to generate a very slow
square wave output with a period between 61.035μs
up to 72.8 hours with 61.035μs resolution. In this
mode, the INT output drives hard both states, rather
than being pulled to one.
• General-purpose comparator interrupt
• A/D conversion complete
• Fan speed control fault (absence of pulses on the
SNSE pin, or duty cycle is 100%) – this is combined
with the general-purpose comparator interrupt
All these interrupts may be individually enabled by seting
the relevant field in the IntEnable register, and cleared
by setting the relevant bit in the IntStatus register. The
INT pin is highly configurable via the AlternateINTFunction
register:
• The INT pin can also be programmed as a general-
purpose I/O port.
Additionally, the general-purpose comparator interrupt
can be programmed to activate on either the rising or fall-
ing edge, so that the interrupt triggers either when the
comparator level rises above its DAC-set threshold, or
when it drops below it, by programming the relevant bit in
the Config register.
The INT output is always hard-driven back to its inactive
state before returning to weak pullup/down, in order to
provide a sharp trailing edge.
• The mode can be specified as level sensitive (the
active level remains until the interrupt has been
cleared), or edge sensitive (a pulse with period equal
to 4 cycles of CLK0, which repeats every time a new
interrupt source is activated, thereby removing the
need to clear periodic interrupts).
Note: The SNSE interrupt can be used as a periodic interrupt
independent from the PIT, because if SNSE is inactive, then
an interrupt is generated every 32768 CLK1 cycles. Therefore
if CLK1 is set for 32.768kHz output (which can of course be
done irrespective of HFDCO setting), then this gives an exact
1Hz interrupt, while still leaving the PIT free.
• The polarity can be programmed – the INT pin is pulled
(weak) inactive, in order that it may be wire-ORed with
any other source, and harddriven to the active state.
• Any individual interrupt can either be cleared by set-
ting the relevant bit(s) in the IntStatus register, or with
a special short-form version of the I²C protocol as de-
scribed in the next section.
© 2006 Semtech Corp.
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