SH3100 Datasheet, PDF (57/80 Pages) Semtech Corporation – Supervisory IC with I2C Interface and PWM

SH3100
POWER MANAGEMENT
Functional Descriptions (continued)
System Reset – Programmable VDD Threshold (VBO)
The SH3100 has two dedicated supervisory functions
that manage the reset of the microcontroller, a low VDD
monitor (Brownout Detector) with programmable thresh-
old (VBO) and a Watchdog Timer with programmable time-
out. Both functions are integrated with the Clock Manage-
ment System to provide a more complete solution than
with standalone components. The SH3100 NRST output
pin is active Low with strong drive to the active state and
weak drive to the inactive state. This eliminates the need
for an external pull-up and allows the NRST pin to be con-
nected in common with other reset sources in a wired-OR
configuration.
During power-up, the NRST pin is guaranteed to be cor-
rectly asserted by the time VDD reaches 1V. It then stays
asserted until VDD exceeds the programmed VDD thresh-
old (VBO) + hysteresis, at which point the SH3100 enters
the power up routine with the appropriate sequencing of
clock start and NRST negation as determined by the pro-
grammable reset duration setting. Flags in the register
map indicate the cause of reset to the microcontroller.
Once powered up, the SH3100 continuously monitors
VDD and generates a system reset on the NRST pin if VDD
drops below VBO. VBO is set by a 7-bit control code to be
between 1.7V and 4V with 24mV resolution. When VDD
drops below VBO, this is defined as a brownout event, and
if VBAK is present, the chip switches to battery backup
mode to maintain register contents and RTC operation
at very low current consumption. If VBAK is not present,
backup mode operation continues to run from VDD until
VDD drops below 1V.
Note: If VDD is likely to collapse very quickly to GND (Less
than 100μs) then it is advisable to add an external 100 nF
decoupling capacitor on VREG to maintain register contents
while the chip changes over to battery backup mode.
The default VBO setting is loaded from nonvolatile memo-
ry on power up, but once the chip has come out of reset,
it may be changed to any other value using an I²C access,
or it can be permanently protected from any changes by
setting the VBO lock flag or the write protect flag. To avoid
the system jumping in and out of reset for noisy VDD levels
near VBO, there is hysteresis on the reset function. When
VDD is falling, NRST asserts at VBO. When VDD is rising,
NRST negates at VBO plus the hysteresis (Vhys). There is
also internal filtering on the VDD comparator which is set
to allow rapid detection of a collapsing VDD while reject-
ing VDD noise spikes of less than a certain duration and
amplitude as shown by the diagram to follow:
Parameter
Symbol
Min
Typ
Max
Units
VBO for Min code (000 0000)
VBOmin
1.65
1.7
1.75
V
VBO for Max code (101 1110)
VBOmax
3.95
4
4.05
V
VDD Hysteresis
Vhys
25
100
mV
VDD falling to NRST asserted delay
Td
5
μs
VBO resolution
Vres
20
24
28
mV
New VBO settling time
Tvbo
4
ms
© 2006 Semtech Corp.
57
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