SH3100 Datasheet, PDF (72/80 Pages) Semtech Corporation – Supervisory IC with I2C Interface and PWM

POWER MANAGEMENT
Functional Descriptions (continued)
Combined Read Format
• Start condition (falling edge on SDA while SCL is high)
to commence the access to the register address to
the SH3100
• 7-bit slave address on SDA, clocked in by SCL
• 1-bit read/write indicator, set low because the follow-
ing 8 bits are the register address, written into the
SH3100
• SH3100 generates ACK pulse to acknowledge slave
address
• 8-bit register address
• SH3100 generates ACK pulse to confirm register ad-
dress transfer
• Restart condition to commence the access to read
from the register address set up by the last access
• 7-bit slave address
• 1-bit read/write indicator, set high because the follow-
ing 8 bits are the read data (payload)
• SH3100 generates ACK pulse to acknowledge slave
address, and may stretch SCL by holding it low for up
to 62 μs if reading the LSB of the RTC or PIT registers
• SH3100 generates 8-bit read data
• The microcontroller can generate either an ACK or
NACK pulse – this is ignored by SH3100
• Stop condition (rising edge on SDA while SCL is high)
Note: If the I²C master (microcontroller) does not support SCL
stretching, and can not be modified to do so, then the RTC
subseconds register (address 0x11) and the PIT LSB (address
0x09) may be read incorrectly. All other reads and writes suc-
ceed, provided CLK0 is running reasonably fast compared to
SCL, i.e. CLK0 frequency is >= 4xSCL frequency.
© 2006 Semtech Corp.
72
SH3100
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