SH3100 Datasheet, PDF (77/80 Pages) Semtech Corporation – Supervisory IC with I2C Interface and PWM

POWER MANAGEMENT
Functional Descriptions (continued)
CLK0 & CLK1 Outputs
Once the HFDCO frequency has been set to between 8
MHz and 33.5MHz, it can be driven out on CLK0 and
CLK1 via independent postscalers.
The CLK0 postscaler is 3 bits and allows division ratios
between 1 and 128 in binary geometric progression. This
allows output frequencies between 62.5kHz and 33.5MHz
with between 250ppm and 60ppm resolution.
The CLK1 postscaler is 4 bits and allows division ratios be-
tween 1 and 32768 in binary geometric progression. This
allows output frequencies between 244Hz and 33.5MHz
with between 250ppm and 60ppm resolution.
CLK0 is treated as the master clock and would usually
be used as the main clock source to the microcontroller.
CLK1 is the secondary clock and may be used for any pur-
pose.
Both CLK0 and CLK1 may also be set to use the internal
32.768kHz clock source. This allows a clock output to be
maintained while the HFDCO is shutdown or during bat-
tery backup.
Both CLK0 and CLK1 output pads may be powered from
either VDD or VBAK in normal operation. If CLK1 is set to
use the internal 32.768kHz clock source, then the supply
automatically switches over to VBAK during battery back-
up. If it is set to a HFDCO derived frequency, then it stops.
CLK0 is always stopped during battery backup.
If spread spectrum is enabled, then the percentage of fre-
quency spreading remains constant, as the native HFDCO
frequency is divided down by the postcaler.
© 2006 Semtech Corp.
77
SH3100
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