SH3100 Datasheet, PDF (49/80 Pages) Semtech Corporation – Supervisory IC with I2C Interface and PWM

SH3100
POWER MANAGEMENT
Applications Information (continued)
Standard Operation - VDD Settles at less than the
Programmed VBO
1. The general-purpose DAC/comparator block and PWM
outputs are disabled.
2. Since VDD is less than the new VBO threshold, the chip
is held in brownout until VDD exceeds VBO.
3. nRST is held asserted.
4. If an external crystal is connected, the logic monitors
the output from the crystal oscillator clock. Once 1024
cycles have been observed to indicate that it is running
in stable operation, the logic switches over to run on the
crystal clock and shuts down the internal oscillator. When
the SH3100 comes out of reset, the HFDCO starts in FLL
locked mode and smoothly pulls into lock after starting
at the HFDCO programmed frequency. If the crystal
oscillator does not start within ten seconds of power-up,
the crystal oscillator circuitry is disabled to save power.
5. Battery backup facility is disabled until the chip has
come out of reset.
Automatic Fan Speed Control Enabled
1. The general-purpose 8-bit DAC and comparator are
enabled. SNSE transition threshold defaults to 70mV.
PWM output is enabled. The VBO Reset duration defaults
to the fuse register setting.
2. Internal temperature is measured at one second
intervals. Fan speed control based on the default
automatic settings is enabled. If no pulses are detected
on SNSE, then the chip enters fan control fault condition
mode.
3. Once VDD passes the VBO threshold, the normal Reset
timer sequence is started. If VDD stays below VBO, then
automatic fan control continues to run, but the HFDCO
remains disabled, resulting in low power consumption
(< 10μA).
4. Once VDD exceeds VBO, CLK0 starts at its programmed
rate, and the micro controller may communicate with the
SH3100. CLK0 and the HFDCO may then be turned off if
required to save power.
5. The micro controller may also modify any of the default
fan speed control settings if required, or change from
automatic mode to manual mode.
6. If VDD then drops below VBO, NRST is asserted but
fan control continues to run until VDD collapses below
approximately 1V. If a watchdog reset occurs, then fan
control continues during the reset condition.
© 2006 Semtech Corp.
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