SH3100 Datasheet, PDF (76/80 Pages) Semtech Corporation – Supervisory IC with I2C Interface and PWM

SH3100
POWER MANAGEMENT
Functional Descriptions (continued)
Clock Management & Frequency Locked Loop (FLL)
FLL Operation
Fast FLL Lock
The HFDCO is used as the master high frequency clock
source on the SH3100. Since this is a free running os-
cillator with a process dependent correlation between
control code and frequency, it is necessary to employ a
frequency locked loop (FLL) to generate an output clock
which is a set multiple of the crystal reference. In opera-
tion, the 32.768kHz crystal clock is divided by 16 to yield
an accurate 2048Hz reference. The HFDCO clock cycles
are counted over the duration of one reference cycle and
compared against the 14-bit FLLDivRatio register to as-
sess whether the HFDCO is running faster or slower than
required. The 19-bit HFDCO code is then incremented or
decremented accordingly. The exact relationship is:
HFDCO Frequency = 2048Hz x (FLLDivRatio + 1)
On an unprogrammed device, or if a new FLL frequency
setting has been programmed into the FLLDivRatio reg-
ister, the FLL can perform a fast locking algorithm using
a successive approximation technique. This is initiated
by setting the Initiate FLLCoarseFreqLock bit of the FLL-
Config register. Once locked, the HFDCO control code may
then be stored for future reference by the system or in the
case of an unprogrammed device, it can be stored in the
register as the default startup code for the HFDCO.
Note: FLL fast lock causes temporary coarse frequency excur-
sions for approximately 25ms until the frequency is locked. To
avoid exposing the microcontroller to these frequency excur-
sions, the locking procedure can be performed while CLK0 is
programmed for 32.768kHz by setting the ForceDCOOn bit of
the Config register.
The frequency select register (FLLDivRatio) is loaded from
its register on power up but can be overwritten by I²C ac-
cess.
On power-up, the FLL automatically starts once the crys-
tal oscillator is stable. If no crystal is present, then the
FLL does not automatically start, but may be initialized by
setting the FLLEnable bit of the FLLConfig register. In this
case, since the crystal is not present, the FLL locks to the
internal 32.768kHz oscillator, but since this has an intrin-
sic free-running accuracy of ±3%, this would result in less
accuracy than the intrinsic ±0.5% free-running accuracy
of the HFDCO. The only reason for doing this would be to
find the approximate HFDCO code for a new frequency in
the absence of an accurate crystal reference.
Fine frequency acquisition can also be initiated with the
InitiateFineFreqLock bit of the FLLConfig register. This
performs successive approximation on only the LSB bank
of the HFDCO, so it can be used to give a smoother rap-
id lock for smaller frequency deviations, such as those
caused by a large temperature change during a shutdown
period when the HFDCO and FLL are disabled.
If the spread spectrum function is enabled, it is temporar-
ily disabled while Coarse or Fine lock are in process, and
is re-enabled once FLL lock is achieved.
The HFDCO code is directly accessible for read and write
by the I²C interface. With the FLL disabled, a microcon-
troller could perform its own locking algorithm if desired.
On a programmed device, the HFDCO starts up within
±0.5% of the desired frequency and the FLL then pulls
the frequency smoothly into lock.
The state of the FLL can be determined by reading the
status register. The FLLLocked bit is set when the FLL is
locked. This is once the FLL has been stable for three con-
secutive measurement cycles (i.e., no more than three
frequency adjustments in the same direction over three
consecutive reference cycles).
Note: The FLLLocked indicator is invalid if the spread spec-
trum function is enabled.
© 2006 Semtech Corp.
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