SH3100 Datasheet, PDF (50/80 Pages) Semtech Corporation – Supervisory IC with I2C Interface and PWM

SH3100
POWER MANAGEMENT
Applications Information (continued)
Switching Regulator Modes Enabled
1. The general-purpose 8-bit DAC and comparator and
PWM outputs are enabled. The SNSE input is made
available for regulator feedback if required. The VBO
Reset duration defaults to the fuse register setting.
2. The appropriate selection of internal circuitry is chosen
for the desired regulator configuration.
3. Since the switching regulator requires a high frequency
clock for operation, the HFDCO is enabled at its
programmed rate even if VDD is still below the VBO
threshold. CLK0 and CLK1 outputs are not enabled until
VDD exceeds VBO.
4. During power up, the PWM pin is set high impedance
and its state is monitored during power-on-reset. If it is
detected as being pulled High externally and the mode
select is bootstrap boost, then this indicates that there
is an inductor from PWM to an external supply and that
internal FET switching is required. Once this is detected,
the PMOS between PWM and VDD is turned on which
clamps VDD to the external supply via the inductor so
allowing boost regulation to start for external supply
inputs of 1.8 V or above. Until the PMOS is turned on,
VDD is approximately one diode voltage below the
external supply as it is powered through the diode from
PWM to VDD. This detection process also allows the
control circuitry to know to set PWM active low during
the inductor energize period. If PWM is detected as Low
during power up, this indicates that an external switching
FET is being used and PWM is set High during the inductor
energize period.
5. HFDCO is enabled periodically as required by the control
logic to maintain regulation.
6. If switching regulator mode is turned off by the micro
controller, then VDD drops. If it drops below the VBO,
then NRST is asserted, and HFDCO is turned off. If VBAK
is high enough, then the chip goes into battery backup
mode. If VBAK is not present, then the chip enters power-
on-reset when VDD drops to approximately 0.9V, and
if VDD rises again, the chip reloads the mode settings
from the fuses and tries to repeat the switching regulator
startup sequence. If VBAK is present and VBAK drops
below 0.9V, the chip switches back on to VDD. If VDD is
above 1.8V at this point, the regulator start-up sequence
begins again.
7. If the external supply drops so low that VDD can not
be maintained above 1.7V, then the HFDCO clock is
disabled and regulation stops. VDD may then collapse
down to below the power-on-reset level.
© 2006 Semtech Corp.
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