SH3100 Datasheet, PDF (58/80 Pages) Semtech Corporation – Supervisory IC with I2C Interface and PWM

SH3100
POWER MANAGEMENT
Functional Descriptions (continued)
Programmable Reset Duration
The programmable reset duration is set by a combination
ofv a single pin and a 5-bit nonvolatile memory (fuse)
register. In normal operating mode the state of the SNSE
pin determines the reset duration as follows:
• If SNSE is connected to GND, then the minimum reset
duration of 6ms is selected.
• If SNSE is floating, then an intermediate reset duration
of 270ms is selected.
• If SNSE is connected to VREG, then the reset dura-
tion as set by the register is selected.
If the SH3100 is operating in one of the non standard
modes then the reset duration defaults to the register
setting.
The reset duration is defined as the time from the end of
a reset condition until NRST is negated.
NRST is always asserted immediately at the start of a
reset event. Regardless of its programmed frequency,
CLK0 continues to run at approximately 700kHz for 2ms
after NRST is asserted. This is in case the microcontroller
needs a few clock cycles to tidy up internal registers after
reset starts. In the case of reset caused by rapidly falling
VDD, CLK0 stops if VDD drops below 1.7V during the 2ms
of the post-NRST-assert period.
Note 1: CLK0 always starts at the programmed rate 4 ms after
the end of a reset condition. This is to ensure that the micro-
controller has a clock source running before NRST is negated.
Some microcontrollers, which use PLL clock multiplication to
generate internal clocks from CLK0, may need a long time to
lock onto CLK0, therefore they need a reset duration greater
than the lock time of their internal PLL multiplier.
Note 2: When a brownout reset condition occurs, the start-up
sequence timer can not start until after a time equal to the
programmed reset duration has elapsed. This means that for
very short brownout events, the observed reset duration on
NRST is double the programmed reset duration.
Note 3: Reset events caused by watchdog timeout or watch-
dog violation also result in NRST being asserted for double the
programmed reset duration.
Note 4: On initial power-up, once VDD exceeds VBO, NRST
stays asserted for the programmed reset duration.
Note 5: If a new reset duration is loaded which is larger than
the current reset duration, this immediately triggers a pro-
grammed reset at the new duration. When the reset ends, the
new duration is effective for further resets.
Note 6: These reset durations are dependent on the accuracy
of the internal 32.268kHz system clock, which may vary by up
to ±3% from the stated figures.
The mapping between the register setting and Reset duration is as follows:
Code
0
1
2
3
4
5
6
7
Duration
6
12
18
24
30
42
54
66
Code
8
9
10
11
12
13
14
15
Duration
78
102
126
150
174
222
270
318
Code
16
17
18
19
20
21
22
23
Duration
366
462
558
654
750
942
1134
1326
Code
24
25
26
27
28
29
30
31
Duration
1518
1902
2286
2670
3054
3822
4590
5358
© 2006 Semtech Corp.
58
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