SH3100 Datasheet, PDF (61/80 Pages) Semtech Corporation – Supervisory IC with I2C Interface and PWM

POWER MANAGEMENT
Functional Descriptions (continued)
Periodic Interval Timer (PIT)
The PIT is clocked at 32.768kHz. The interval timer uses
the 32-bit WakeUpTime register as its ultimate count val-
ue. Although the timer continues to run, the interrupt re-
mains active until reset by software. The timer is disabled
at power up until the period is initialized.
Period = WakeUpTime/32768 to give a range of 30.5μs
up to 36.4 hours with 30.5μs resolution, subject to the
tolerance of the crystal or internal oscillator.
For synchronization purposes the PIT should be read LSB
first – this causes all four bytes to be latched into a shad-
ow register in the SerialIF simultaneously in order to avoid
problems of byte-overflow between individual byte-reads.
The PIT counter can not be written directly, but is reset
whenever the LSB of the WakeUpTime register is written
to start a fresh period. The WakeupTime register should
be written MSB first, and only when the LSB is written are
the entire four bytes loaded into the WakeupTime register
in the PIT block.
Note: The WakeupTime register remains throughout brown-
out and WDT events, and may be used as a general pur-
pose scratchpad, if not used for its primary purpose.
Because the PIT shares a shadow register with the RTC
and DCOCode, and the same register is used for both
reads and writes, it is important that none of these regis-
ters are accessed within one period of the last timer writ-
ten to (therefore 31μs after the wakeup time has been
updated, or 4ms after the RTC has been written, or imme-
diately after the HFDCO has been written).
© 2006 Semtech Corp.
61
SH3100
www.semtech.com