K4R271669A Datasheet, PDF (62/64 Pages) Samsung semiconductor – 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R271669A/K4R441869A
Direct RDRAM^™
NOXOP
No-operation command in XOP field.
NSR
INIT register field- NAP self-refresh.
packet
A collection of bits carried on the Channel.
PDN
Power state - needs SCK/CMD wakeup.
PDNR
Powerdown command in ROP field.
PDNXA
Control register - PDN exit delay A.
PDNXB
Control register - PDN exit delay B.
pin efficiency The fraction of non-idle cycles on a pin.
PRE
PREC,PRER,PREX precharge commands.
PREC
Precharge command in COP field.
precharge Prepares sense amp and bank for activate.
PRER
Precharge command in ROP field.
PREX
Precharge command in XOP field.
PSX
INIT register field - PDN/NAP exit.
PSR
INIT register field - PDN self-refresh.
PVER
CNFGB register field - protocol version.
Q
Read data packet on DQ pins.
R
Row address field of ROWA packet.
RBIT
CNFGB register field - # row address bits.
RD/RDA
Read (/precharge) command in COP field.
read
Operation of accesssing sense amp data.
receive
Moving information from the Channel into
the RDRAM (a serial stream is demuxed).
REFA
Refresh-activate command in ROP field.
REFB
Control register - next bank (self-refresh).
REFBIT
CNFGA register field - ignore bank bits
(for REFA and self-refresh).
REFP
Refresh-precharge command in ROP field.
REFR
Control register - next row for REFA.
refresh
Periodic operations to restore storage cells.
retire
The automatic operation that stores write
buffer into sense amp after WR command.
RLX
RLXC,RLXR,RLXX relax commands.
RLXC
Relax command in COP field.
RLXR
Relax command in ROP field.
RLXX
Relax command in XOP field.
ROP
row
Row-opcode field in ROWR packet.
2^CBIT dualocts of cells (bank/sense amp).
ROW
Pins for row-access control
ROW
ROWA or ROWR packets on ROW pins.
ROWA
Activate packet on ROW pins.
ROWR
RQ
RSL
SAM
SA
SBC
SCK
SD
SDEV
SDEVID
self-refresh
sense amp
SETF
SETR
SINT
SIO0,SIO1
SOP
SRD
SRP
SRQ
STBY
SVER
SWR
TCAS
TCLS
TCLSCAS
TCYCLE
TDAC
TEST77
TEST78
TRDLY
transaction
transmit
WR/WRA
write
XOP
Row operation packet on ROW pins.
Alternate name for ROW/COL pins.
Rambus Signaling Levels.
Sample (I_OL) command in XOP field.
Serial address packet for control register
transactions w/ SA address field.
Serial broadcast field in SRQ.
CMOS clock pin.
Serial data packet for control register
transactions w/ SD data field.
Serial device address in SRQ packet.
INIT register field - Serial device ID.
Refresh mode for PDN and NAP.
Fast storage that holds copy of bank’s row.
Set fast clock command from SOP field.
Set reset command from SOP field.
Serial interval packet for control register
read/write transactions.
CMOS serial pins for control registers.
Serial opcode field in SRQ.
Serial read opcode command from SOP.
INIT register field - Serial repeat bit.
Serial request packet for control register
read/write transactions.
Power state - ready for ROW packets.
Control register - stepping version.
Serial write opcode command from SOP.
TCLSCAS register field - t_CAS core delay.
TCLSCAS register field - t_CLS core delay.
Control register - t_CAS and t_CLS delays.
Control register - t_CYCLE delay.
Control register - t_DAC delay.
Control register - for test purposes.
Control register - for test purposes.
Control register - t_RDLY delay.
ROW,COL,DQ packets for memory
access.
Moving information from the RDRAM
onto the Channel (parallel word is muxed).
Write (/precharge) command in COP field.
Operation of modifying sense amp data.
Extended opcode field in COLX packet
Page 60
Rev. 1.02 Jan. 2000