K4R271669A Datasheet, PDF (12/64 Pages) Samsung semiconductor – 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R271669A/K4R441869A
Direct RDRAM^™
DQ Packet Timing
Figure 4 shows the timing relationship of COLC packets
with D and Q data packets. This document uses a specific
convention for measuring time intervals between packets: all
packets on the ROW and COL pins (ROWA, ROWR,
COLC, COLM, COLX) use the trailing edge of the packet as
a reference point, and all packets on the DQA/DQB pins (D
and Q) use the leading edge of the packet as a reference
point.
An RD or RDA command will transmit a dualoct of read
data Q a time t_CAC later. This time includes one to five
cycles of round-trip propagation delay on the Channel. The
t_CAC parameter may be programmed to a one of a range of
values ( 8, 9, 10, 11, or 12 t_CYCLE). The value chosen
depends upon the number of RDRAM devices on the
Channel and the RDRAM timing bin. See Figure 39 for
more information.
A WR or WRA command will receive a dualoct of write
data D a time t_CWD later. This time does not need to include
the round-trip propagation time of the Channel since the
COLC and D packets are traveling in the same direction.
When a Q packet follows a D packet (shown in the left half
of the figure), a gap (t_CAC -t_CWD) will automatically appear
between them because the t_CWD value is always less than the
t_CAC value. There will be no gap between the two COLC
packets with the WR and RD commands which schedule the
D and Q packets.
When a D packet follows a Q packet (shown in the right half
of the figure), no gap is needed between them because the
t_CWD value is less than the t_CAC value. However, , a gap of
t_CAC -t_CWD or greater must be inserted between the COLC
packets with the RD WR commands by the controller so the
Q and D packets do not overlap.
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂T₁₃ T₁₄ T₁₅ T₁₆T₁₇ T₁₈ T₁₉ T₂₀T₂₁ T₂₂ T₂₃ T₂₄T₂₅ T₂₆ T₂₇ T₂₈T₂₉ T₃₀ T₃₁ T₃₂T₃₃ T₃₄ T₃₅ T₃₆T₃₇ T₃₈ T₃₉ T₄₀T₄₁ T₄₂ T₄₃ T₄₄T₄₅ T₄₆ T₄₇
CTM/CFM
ROW2
..ROW0
COL4
..COL0
DQA8..0
DQB8..0
This gap on the DQA/DQB pins appears automatically
WR a1
t_CWD
RD b1
t_CAC -t_CWD
•••
D (a1)
Q (b1)
Q (b1)
Q (a1)
Q (Qa1()a1)
t_CAC
•••
This gap on the COL pins must be inserted by the controller
t_CAC-t_CWD
RD c1
• • • _WRWdR1WdR1 ^d1
WR d1
WR d1
t_CWD
•••
Q (c1)
Q (c1)
D (Dd1()d1)
Q (Qc1)(c1) D (Dd1()d1)
Q (a1) D (d1)
•••
t_CAC
Figure 4: Read (Q) and Write (D) Data Packet - Timing for t_CAC = 8, 9, 10, 11, or 12 t_CYCLE
COLM Packet to D Packet Mapping
Figure 5 shows a write operation initiated by a WR
command in a COLC packet. If a subset of the 16 bytes of
write data are to be written, then a COLM packet is trans-
mitted on the COL pins a time t_RTR after the COLC packet
containing the WR command. The M bit of the COLM
packet is set to indicate that it contains the MA and MB
mask fields. Note that this COLM packet is aligned with the
COLC packet which causes the write buffer to be retired.
See Figure 17 for more details.
housekeeping command (this case is not shown). The M bit
is not asserted in an COLX packet and causes all 16 bytes of
the previous WR to be written unconditionally. Note that a
RD command will never need a COLM packet, and will
always be able to use the COLX packet option (a read opera-
tion has no need for the byte-write-enable control bits).
Figure 5 also shows the mapping between the MA and MB
fields of the COLM packet and bytes of the D packet on the
DQA and DQB pins. Each mask bit controls whether a byte
of data is written (=1) or not written (=0).
If all 16 bytes of the D data packet are to be written, then no
further control information is required. The packet slot that
would have been used by the COLM packet (t_RTR after the
COLC packet) is available to be used as an COLX packet.
This could be used for a PREX precharge command or for a
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Rev. 1.02 Jan. 2000