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K4R271669A Datasheet, PDF (21/64 Pages) Samsung semiconductor – 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
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K4R271669A/K4R441869A
Direct RDRAM™
COLC Packet: RDA Precharge Offset
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12T13 T14 T15 T16T17 T18 T19 T20T21 T22 T23 T24T25 T26 T27 T28T29 T30 T31 T32T33 T34 T35 T36T37 T38 T39 T40T41 T42 T43 T44T45 T46 T47
CTM/CFM
ROW2
..ROW0
COL4
..COL0
The RDA precharge is equivalent to a PRER command here
ACT a0
PRER a5
ACT b0
RD a1 RD a2 RD a3 RDA a4
tOFFP
DQA8..0
DQB8..0
Transaction a: RD a0 = {Da,Ba,Ra}
COLC Packet: WDA Precharge Offset
Q (a1) Q (a2) Q (a3) Q (a4)
a1 = {Da,Ba,Ca1}
a3 = {Da,Ba,Ca3}
a2 = {Da,Ba,Ca2}
a4 = {Da,Ba,Ca4}
a5 = {Da,Ba}
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12T13 T14 T15 T16T17 T18 T19 T20T21 T22 T23 T24T25 T26 T27 T28T29 T30 T31 T32T33 T34 T35 T36T37 T38 T39 T40T41 T42 T43 T44T45 T46 T47
CTM/CFM
ROW2
..ROW0
COL4
..COL0
The WRA precharge (triggered by the automatic retire) is equivalent to a PRER command here
ACT a0
PRER a5
ACT b0
WR a1
WRA a2
tRTR
retire (a1) retire (a2)
MSK (a1) MSK (a2)
tOFFP
DQA8..0
DQB8..0
D (a1) D (a2)
Transaction a: WR a0 = {Da,Ba,Ra}
a1 = {Da,Ba,Ca1}
a2 = {Da,Ba,Ca2}
a5 = {Da,Ba}
COLX Packet: PREX Precharge Offset
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12T13 T14 T15 T16T17 T18 T19 T20T21 T22 T23 T24T25 T26 T27 T28T29 T30 T31 T32T33 T34 T35 T36T37 T38 T39 T40T41 T42 T43 T44T45 T46 T47
CTM/CFM
ROW2
..ROW0
COL4
..COL0
The PREX precharge command is equivalent to a PRER command here
ACT a0
PRER a5
ACT b0
RD a1
RD a2
RD a3 RD a4
PREX a5
tOFFP
DQA8..0
DQB8..0
Q (a1) Q (a2) Q (a3) Q (a4)
Transaction a: RD a0 = {Da,Ba,Ra}
a1 = {Da,Ba,Ca1}
a3 = {Da,Ba,Ca3}
a2 = {Da,Ba,Ca2}
a4 = {Da,Ba,Ca4}
Figure 14: Offsets for Alternate Precharge Mechanisms
a5 = {Da,Ba}
Page 19
Rev. 1.02 Jan. 2000
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