K4R271669A Datasheet, PDF (54/64 Pages) Samsung semiconductor – 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R271669A/K4R441869A
Direct RDRAM^™
CMOS - Transmit Timing
Figure 58 is a timing diagram which shows the detailed
requirements for the CMOS output signals. The SIO0 signal
is driven once per t_CYCLE1 interval on the falling edge. The
SCK
clock-to-output window is t_Q1,MIN/t_Q1,MAX. The SCK and
SIO0 timing points are measured at the 50% level. The rise
and fall times of SIO0 are t_QR1 and t_QF1, measured at the
20% and 80% levels.
V_IH,CMOS
80%
50%
SIO0
t_Q1,MAX
t_HR,MIN
t_QR1
20%
V_IL,CMOS
V_OH,CMOS
80%
50%
t_QF1
SIO0
or
SIO1
t_DR1
20%
V_OL,CMOS
V_IH,CMOS
80%
50%
t_DF1
SIO1
or
SIO0
t_PROP1,MAX
t_PROP1,MIN
t_QR1
20%
V_IL,CMOS
V_OH,CMOS
80%
50%
t_QF1
Figure 58: CMOS Timing - Data Signals for Transmit
20%
V_OL,CMOS
Page 52
Rev. 1.02 Jan. 2000