K4R271669A Datasheet, PDF (56/64 Pages) Samsung semiconductor – 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R271669A/K4R441869A
Timing Parameters
Direct RDRAM^™
Table 22: Timing Parameter Summary
Parameter Description
Min Min Min
-45 -45 -53.3 Max
-800 -711 -600
Units Figure(s)
t_RC
Row Cycle time of RDRAM banks -the interval between ROWA packets with 28
28
28
-
t_CYCLE Figure 15
ACT commands to the same bank.
Figure 16
t_RAS
RAS-asserted time of RDRAM bank - the interval between ROWA packet
20
20
20
64µs^b t_CYCLE Figure 15
with ACT command and next ROWR packet with PRER^a command to the
Figure 16
same bank.
t_RP
Row Precharge time of RDRAM banks - the interval between ROWR packet 8
8
8
-
t_CYCLE Figure 15
with PRER^a command and next ROWA packet with ACT command to the
Figure 16
same bank.
t_PP
Precharge-to-precharge time of RDRAM device - the interval between succes- 8
8
8
-
t_CYCLE Figure 12
sive ROWR packets with PRER^a commands to any banks of the same device.
t_RR
RAS-to-RAS time of RDRAM device - the interval between successive
ROWA packets with ACT commands to any banks of the same device.
8
8
8
-
t_CYCLE Figure 13
t_RCD
RAS-to-CAS Delay - the interval from ROWA packet with ACT command to 9
7
7
-
t_CYCLE Figure 15
COLC packet with RD or WR command). Note - the RAS-to-CAS delay seen
Figure 16
by the RDRAM core (t_RCD-C) is equal to t_RCD-C = 1 + t_RCD because of differ-
ences in the row and column paths through the RDRAM interface.
t_CAC
t_CWD
t_CC
CAS Access delay - the interval from RD command to Q read data. The equa- 8
8
8
12
t_CYCLE Figure 4
tion for t_CAC is given in the TPARM register in Figure 39.
Figure 39
CAS Write Delay (interval from WR command to D write data.
6
6
6
6
t_CYCLE Figure 4
CAS-to-CAS time of RDRAM bank - the interval between successive COLC 4
4
4
commands).
-
t_CYCLE Figure 15
Figure 16
t_PACKET Length of ROWA, ROWR, COLC, COLM or COLX packet.
4
4
4
t_RTR
Interval from COLC packet with WR command to COLC packet which causes 8
8
8
retire, and to COLM packet with bytemask.
4
t_CYCLE Figure 3
-
t_CYCLE Figure 17
t_OFFP
The interval (offset) from COLC packet with RDA command, or from COLC 4
4
4
packet with retire command (after WRA automatic precharge), or from COLC
packet with PREC command, or from COLX packet with PREX command to
the equivalent ROWR packet with PRER. The equation for t_OFFP is given in
the TPARM register in Figure 39.
4
t_CYCLE Figure 14
Figure 39
t_RDP
Interval from last COLC packet with RD command to ROWR packet with
4
4
4
-
t_CYCLE Figure 15
PRER.
t_RTP
Interval from last COLC packet with automatic retire command to ROWR
4
4
4
-
t_CYCLE Figure 16
packet with PRER.
a. Or equivalent PREC or PREX command. See Figure 14.
b. This is a constraint imposed by the core, and is therefore in units of µs rather than t_CYCLE.
Page 54
Rev. 1.02 Jan. 2000