K4R271669A Datasheet, PDF (37/64 Pages) Samsung semiconductor – 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R271669A/K4R441869A
Direct RDRAM^™
Control Register: NAPX
Address: 045₁₆
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 DQS
NAPX4..0
NAPXA4..0
.
Read/write register.
Reset value is undefined
Note - t_SCYCLE is t_CYCLE1 (SCK cycle time).
NAPXA4..0 - Nap Exit Phase A. This field specifies
the number of SCK cycles during the first phase for
exiting NAP mode. It must satisfy:
NAPXA•t _SCYCLE ≥ t_NAPXA,MAX
Do not set this field to zero.
NAPX4..0 - Nap Exit Phase A plus B. This field specifies the number of SCK
cycles during the first plus second phases for exiting NAP mode. It must satisfy:
NAPX•t _SCYCLE ≥ NAPXA•t _SCYCLE+t_NAPXB,MAX
Do not set this field to zero.
DQS - DQ Select. This field specifies the number of SCK cycles (0 => 0.5
cycles, 1 => 1.5 cycles) between the CMD pin framing sequence and the device
selection on DQ5..0. See Figure 48 - This field must be written with a ″1″ for
this RDRAM.
Figure 36: NAPX Register
Control Register: PDNXA
Address: 046₁₆
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
000
PDNXA12..0
Control Register: PDNX
Address: 047₁₆
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
000
PDNX12..0
Read/write register.
Reset value is undefined
PDNXA4..0 - PDN Exit Phase A. This field specifies
the number of (64•SCK cycle) units during the first
phase for exiting PDN mode. It must satisfy:
PDNXA•64•t _SCYCLE ≥ t_PDNXA,MAX
Do not set this field to zero.
Note - only PDNXA5..0 are implemented.
Note - t_SCYCLE is t_CYCLE1 (SCK cycle time).
Figure 37: PDNXA Register
Read/write register.
Reset value is undefined
PDNX4..0 - PDN Exit Phase A plus B. This field spec-
ifies the number of (256•SCK cycle) units during the
first plus second phases for exiting PDN mode. It must
satisfy:
PDNX•256•t _SCYCLE ≥ PDNXA•64•t _SCYCLE+
t_PDNXB,MAX
If this equation can’t be satisfied, then the maximum
PDNX value should be written, and the t_S4/t_H4 timing
window will be modified (see Figure 49)
Do not set this field to zero.
Note - only PDNX2..0 are implemented.
Note - t_SCYCLE is t_CYCLE1 (SCK cycle time).
Figure 38: PDNX Register
Page 35
Rev. 1.02 Jan. 2000