K4R271669A Datasheet, PDF (30/64 Pages) Samsung semiconductor – 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R271669A/K4R441869A
Initialization
T₀
SCK
T₁₆
1
0
1
CMD
00001100
00000000...00000000
0
SIO0
SIO1
1
0000000000000000
0
The packet is repeated
from SIO0 to SIO1
1
0000000000000000
0
Figure 26: SIO Reset Sequence
Initialization refers to the process that a controller must go
through after power is applied to the system or the system is
reset. The controller prepares the RDRAM sub-system for
normal Channel operation by using a sequence of control
register transactions on the serial CMOS pins.The following
steps outline the sequence seen by the various memory
subsystem components (including the RDRAM compo-
nents) during initialization. This sequence is available in the
form of reference code.
1.0 Start Clocks - This step calculates the proper clock
frequencies for PClk (controller logic), SynClk (RAC
block), RefClk (DRCG component), CTM (RDRAM
component), and SCK ( SIO block).
2.0 RAC Initialization - This step causes the INIT block to
generate a sequence of pulses which resets the RAC,
performs RAC maintainance operations, and measures
timing intervals in order to ensure clock stability.
3.0 RDRAM Initialization - This stage performs most of
the steps needed to initialize the RDRAMs. The rest are
performed in stages 5.0, 6.0, and 7.0. All of the Steps in 3.0
are carried out through the SIO block interface.
ο 3.1/3.2 SIO Reset - This reset operation is performed
before any SIO control register read or write transactions.
It clears six registers (TEST34, CCA, CCB, SKIP,
TEST78, and TEST79) and places the INIT register into a
special state (all bits cleared except SRP and SDEVID
fields are set to ones).
ο 3.3 Write TEST77 Register - The TEST77 register
must be explicitly written with zeros before any other
registers are read or written.
ο 3.4 Write TCYCLE Register - The TCYCLE register
is written with the cycle time tCYCLE of the CTM clock
Direct RDRAM^™
(for Channel and RDRAMs) in units of 64ps. The
tCYCLE value is determined in stage 1.0.
ο 3.5 Write SDEVID Register - The SDEVID (serial
device identification) register of each RDRAM is written
with a unique address value so that directed SIO read and
write transactions can be performed. This address value
increases from 0 to 31 according to the distance an
RDRAM is from the ASIC component on the SIO bus (
the closest RDRAM is address 0).
ο 3.6 Write DEVID Register - The DEVID (device iden-
tification) register of each RDRAM is written with a
unique address value so that directed memory read and
write transactions can be performed. This address value
increases from 0 to 31. The DEVID value is not neces-
sarily the same as the SDEVID value. RDRAMs are
sorted into regions of the same core configuration
(number of bank, row, and column address bits and core
type).
ο 3.7 Write PDNX, PDNXA Registers - The PDNX and
PDNXA registers are written with values that are used to
measure the timing intervals connected with an exit from
the PDN (powerdown) power state.
ο 3.8 Write NAPX Register - The NAPX register is
written with values that are used to measure the timing
intervals connected with an exit from the NAP power
state.
ο 3.9 Write TPARM Register - The TPARM register is
written with values which determine the time interval
between a COL packet with a memory read command and
the Q packet with the read data on the Channel. The values
written set each RDRAM to the minimum value permitted
for the system. This will be adjusted later in stage 6.0.
ο 3.10 Write TCDLY1 Register - The TCDLY1 register
is written with values which determine the time interval
between a COL packet with a memory read command and
the Q packet with the read data on the Channel. The values
written set each RDRAM to the minimum value permitted
for the system. This will be adjusted later in stage 6.0.
ο 3.11 Write TFRM Register - The TFRM register is
written with a value that is related to the t_RCD parameter
for the system. The t_RCD parameter is the time interval
between a ROW packet with an activate command and the
COL packet with a read or write command.
ο 3.12 SETR/CLRR - Each RDRAM is given a SETR
command and a CLRR command through the SIO block.
This sequence performs a second reset operation on the
RDRAMs.
Page 28
Rev. 1.02 Jan. 2000