K4R271669A Datasheet, PDF (53/64 Pages) Samsung semiconductor – 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R271669A/K4R441869A
Direct RDRAM^™
The SCK clock is also used for sampling data on RSL inputs
in one situation. Figure 48 shows the PDN and NAP exit
sequences. If the PSX field of the INIT register is one (see
Figure 27), then the PDN and NAP exit sequences are broad-
cast; i.e. all RDRAMs that are in PDN or NAP will perform
the exit sequence. If the PSX field of the INIT register is
zero, then the PDN and NAP exit sequences are directed; i.e.
only one RDRAM that is in PDN or NAP will perform the
exit sequence.
The address of that RDRAM is specified on the DQA[5:0]
bus in the set/hold window t_S3/t_H3 around the rising edge of
SCK. This is shown in Figure 57. The SCK timing point is
measured at the 50% level, and the DQA[5:0] bus signals are
measured at the V_REF level.
SCK
V_IH,CMOS
80%
50%
DQA[5:0]
t_S3
t_H3
PDEV
Figure 57: CMOS Timing - Device Address for NAP or PDN Exit
20%
V_IL,CMOS
V_DIH
80%
V_REF
20%
V_DIL
Page 51
Rev. 1.02 Jan. 2000