K4R271669A Datasheet, PDF (32/64 Pages) Samsung semiconductor – 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R271669A/K4R441869A
Direct RDRAM^™
S28IECO=1: Upon powerup the device enters PDN state.
The serial operations SETR, CLRR, and SETF require a
SDEVID match.
See the document detailing the reference initialization proce-
dure for more information on how to handle this in a system.
Initialization Note [3]: After the step of equalizing the total
read delay of each RDRAM has been completed (i.e.after the
TCDLY0 and TCDLY1 fields have been written for the final
time), a single final memory read transaction should be
made to each RDRAM in order to ensure that the output
pipeline stages have been cleared.
Initialization Note [4]: The SETF command (in the serial
SRQ packet) should only be issued once during the Initial-
ization process, as should the SETR and CLRR commands.
Initialization Note [5]: The CLRR command (in the serial
SRQ packet) leaves some of the contents of the memory
core in an indeterminate state.
Control Register Summary
Table 16 summarizes the RDRAM control registers. Detail
is provided for each control register in Figure 27 through
Figure 43. Read-only bits which are shaded gray are unused
and return zero. Read-write bits which are shaded gray are
reserved and should always be written with zero. The RIMM
SPD Application Note describes additional read-only
configuration registers which are present on Direct RIMMs.
The state of the register fields are potentially affected by the
IO Reset operation or the SETR/CLRR operation. This is
indicated in the text accompanying each register diagram.
Table 16: Control Register Summary
SA11..SA0
021₁₆
Register
INIT
022₁₆
023₁₆
TEST34
CNFGA
024₁₆
CNFGB
040₁₆
041₁₆
042₁₆
043₁₆
044₁₆
DEVID
REFB
REFR
CCA
CCB
Field
SDEVID
PSX
SRP
NSR
PSR
LSR
TEN
TSQ
DIS
TEST34
REFBIT
DBL
MVER
PVER
BYT
DEVTYP
SPT
CORG
SVER
DEVID
REFB
REFR
CCA
ASYMA
CCB
ASYMB
read-write/ read-only Description
read-write, 6 bits
read-write, 1 bit
read-write, 1 bit
read-write, 1 bit
read-write, 1 bit
read-write, 1 bit
read-write, 1 bit
read-write, 1 bit
read-write, 1 bit
read-write, 16 bits
read-only, 3 bit
read-only, 1 bit
read-only, 6 bit
read-only, 6 bit
read-only, 1 bit
read-only, 3 bit
read-only, 1 bit
read-only, 6 bit
read-only, 6 bit
read-write, 5 bits
read-write, 4 bits
read-write, 9 bits
read-write, 7 bits
read-write, 2 bits
read-write, 7 bits
read-write, 2 bits
Serial device ID. Device address for control register read/write.
Power select exit. PDN/NAP exit with device addr on DQA5..0.
SIO repeater. Used to initialize RDRAM.
NAP self-refresh. Enables self-refresh in NAP mode.
PDN self-refresh. Enables self-refresh in PDN mode.
Low power self-refresh. Enables low power self-refresh.
Temperature sensing enable.
Temperature sensing output.
RDRAM disable.
Test register. Do not read or write after SIO reset.
Refresh bank bits. Used for multi-bank refresh.
Double. Specifies doubled-bank architecture
Manufacturer version. Manufacturer identification number.
Protocol version. Specifies version of Direct protocol supported.
Byte. Specifies an 8-bit or 9-bit byte size.
Device type. Device can be RDRAM or some other device category.
Split-core. Each core half is an individual dependent core.
Core organization. Bank, row, column address field sizes.
Stepping version. Mask version number.
Device ID. Device address for memory read/write.
Refresh bank. Next bank to be refreshed by self-refresh.
Refresh row. Next row to be refreshed by REFA, self-refresh.
Current control A. Controls I_OL output current for DQA.
Asymmetry control. Controls asymmetry of V_OL/V_OH swing for DQA.
Current control B. Controls I_OL output current for DQB.
Asymmetry control. Controls asymmetry of V_OL/V_OH swing for DQB.
Page 30
Rev. 1.02 Jan. 2000