K4R271669A Datasheet, PDF (59/64 Pages) Samsung semiconductor – 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R271669A/K4R441869A
Direct RDRAM^™
This circuit does not include pin coupling effects that are
often present in the packaged device. Because coupling
effects make the effective single-pin inductance L_I, and
capacitance C_I, a function of neighboring pins, these param-
eters are intrinsically data-dependent. For purposes of speci-
fying the device electrical loading on the Channel, the
effective L_I and C_I are defined as the worst-case values over
all specified operating conditions.
L_I is defined as the effective pin inductance based on the
device pin assignment. Because the pad assignment places
each RSL signal adjacent to an AC ground (a Gnd or Vdd
pin), the effective inductance must be defined based on this
configuration. Therefore, L_I assumes a loop with the RSL
pin adjacent to an AC ground.
C_I is defined as the effective pin capacitance based on the
device pin assignment. It is the sum of the effective package
pin capacitance and the IO pad capacitance.
Table 25: RSL Pin Parasitics
Symbol
Parameter and Conditions - RSL pins
IO freq.
Min
L_I
RSL effective input inductance
L₁₂
Mutual inductance between any DQA or DQB RSL signals.
Mutual inductance between any ROW or COL RSL signals.
∆L_I
Difference in L_I value between any RSL pins of a single device.
-
C_I
RSL effective input capacitance^a
-800
2.0
-711
2.0
-600
2.0
C₁₂
Mutual capacitance between any RSL signals.
-
∆C_I
Difference in C_I value between average of CTM/CFM and any RSL
-
pins of a single device.
R_I
RSL effective input resistance
4
Max
Unit
4.0
nH
0.2
nH
0.6
nH
1.8
nH
2.4
pF
2.4
2.6
0.1
pF
0.06
pF
15
Ω
a. This value is a combination of the device IO circuitry and package capacitances.
Table 26: CMOS Pin Parasitics
Symbol
L_{I ,CMOS}
C_{I ,CMOS}
C_{I ,CMOS,SIO}
Parameter and Conditions - CMOS pins
CMOS effective input inductance
CMOS effective input capacitance (SCK,CMD)^a
CMOS effective input capacitance (SIO1, SIO0)^a
Min
Max
Unit
8.0
nH
1.7
2.1
pF
-
7.0
pF
a. This value is a combination of the device IO circuitry and package capacitances.
Page 57
Rev. 1.02 Jan. 2000