K4R271669A Datasheet, PDF (51/64 Pages) Samsung semiconductor – 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R271669A/K4R441869A
Direct RDRAM^™
RSL - Transmit Timing
Figure 55 is a timing diagram which shows the detailed
requirements for the RSL output signals on the Channel.
The DQA and DQB signals are outputs to transmit informa-
tion that is received by a Direct RAC on the Channel. Each
signal is driven twice per t_CYCLE interval. The beginning
and end of the even transmit window is at the 75% point of
the previous cycle and at the 25% point of the current cycle.
The beginning and end of the odd transmit window is at the
25% point and at the 75% point of the current cycle. These
transmit points are measured relative to the crossing points
of the falling CTM clock edge. The size of the actual
transmit window is less than the ideal t_CYCLE/2, as indicated
by the non-zero values of t_Q,MIN and t_Q,MAX. The t_Q param-
eters are measured at the 50% voltage point of the output
transition.
The t_QR and t_QF rise- and fall-time parameters are measured
at the 20% and 80% points of the output transition.
CTM
CTMN
DQA
DQB
V_X-
0.75•t _CYCLE
t_QR
V_CM
V_X+
t_Q,MAX
0.25•t _CYCLE
0.75•t _CYCLE
t_Q,MAX
t_Q,MIN
even
odd
V_CIH
80%
50%
20%
V_CIL
t_Q,MIN
V_QH
80%
50%
20%
V_QL
t_QF
Figure 55: RSL Timing - Data Signals for Transmit
Page 49
Rev. 1.02 Jan. 2000