K4R271669A Datasheet, PDF(23/64 Page) Samsung semiconductor – 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM

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K4R271669A Datasheet, PDF (23/64 Pages) Samsung semiconductor – 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM

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K4R271669A/K4R441869A

Direct RDRAMâ¢

Write Transaction - Example

Figure 16 shows an example of a write transaction. It begins

by activating a bank with an ACT a0 command in an ROWA

packet. A time tRCD-tRTR later a WR a1 command is issued

in a COLC packet (note that the tRCD interval is measured to

the end of the COLC packet with the first retire command).

Note that the ACT command includes the device, bank, and

row address (abbreviated as a0) while the WR command

includes device, bank, and column address (abbreviated as

a1). A time tCWD after the WR command the write data

dualoct D(a1) is issued. Note that the packets on the ROW

and COL pins use the end of the packet as a timing reference

point, while the packets on the DQA/DQB pins use the

beginning of the packet as a timing reference point.

A time tCC after the first COLC packet on the COL pins a

second COLC packet is issued. It contains a WR a2

command. The a2 address has the same device and bank

address as the a1 address (and a0 address), but a different

column address. A time tCWD after the second WR

command a second write data dualoct D(a2) is issued.

A time tRTR after each WR command an optional COLM

packet MSK (a1) is issued, and at the same time a COLC

packet is issued causing the write buffer to automatically

retire. See Figure 17 for more detail on the write/retire

mechanism. If a COLM packet is not used, all data bytes are

unconditionally written. If the COLC packet which causes

the write buffer to retire is delayed, then the COLM packet

(if used) must also be delayed.

Next, a PRER a3 command is issued in an ROWR packet on

the ROW pins. This causes the bank to precharge so that a

different row may be activated in a subsequent transaction or

so that an adjacent bank may be activated. The a3 address

includes the same device and bank address as the a0, a1, and

a2 addresses. The PRER command must occur a time tRAS

or more after the original ACT command (the activation

operation in any DRAM is destructive, and the contents of

the selected row must be restored from the two associated

sense amps of the bank during the tRAS interval).

A PRER a3 command is issued in an ROWR packet on the

ROW pins. The PRER command must occur a time tRTP or

more after the last COLC which causes an automatic retire.

Finally, an ACT b0 command is issued in an ROWR packet

on the ROW pins. The second ACT command must occur a

time tRC or more after the first ACT command and a time tRP

or more after the PRER command. This ensures that the

bank and its associated sense amps are precharged. This

example assumes that the second transaction has the same

device and bank address as the first transaction, but a

different row address. Transaction b may not be started until

transaction a has finished. However, transactions to other

banks or other devices may be issued during transaction a.

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12T13 T14 T15 T16T17 T18 T19 T20T21 T22 T23 T24T25 T26 T27 T28T29 T30 T31 T32T33 T34 T35 T36T37 T38 T39 T40T41 T42 T43 T44T45 T46 T47

CTM/CFM

ROW2

..ROW0

COL4

..COL0

DQA8..0

DQB8..0

ACT a0

tRCD

WR a1

tRC

PRER a3

ACT b0

tRAS

WR a2 retire (a1) retire (a2)

MSK (a1) MSK (a2)

tRTR

D (a1) D (a2)

tRP

tRTP

Transaction a: WR

Transaction b: xx

tCC

tCWD

a0 = {Da,Ba,Ra}

b0 = {Da,Ba,Rb}

a1 = {Da,Ba,Ca1}

a2 = {Da,Ba,Ca2}

a3 = {Da,Ba}

Figure 16: Write Transaction Example

Page 21

Rev. 1.02 Jan. 2000

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