K4R271669A Datasheet, PDF (42/64 Pages) Samsung semiconductor – 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R271669A/K4R441869A
Direct RDRAM^™
PDEV5..0 address packet and exits NAP or PDN when the
wake-up sequence is presented on the CMD wire. The ROW
and COL pins must be quiet at a time t_S4/t_H4 around the indi-
cated falling SCK edge (timed with the PDNX or NAPX
register fields). After that, ROW and COL packets may be
directed to the RDRAM which is now in ATTN or STBY
state.
Figure 49 shows the constraints for entering and exiting
NAP and PDN states. On the left side, an RDRAM exits
NAP state at the end of cycle T₃. This RDRAM may not re-
enter NAP or PDN state for an interval of t_NU0. The
RDRAM enters NAP state at the end of cycle T₁₃. This
RDRAM may not re-exit NAP state for an interval of t_NU1.
The equations for these two parameters depend upon a
number of factors, and are shown at the bottom of the figure.
NAPX is the value in the NAPX field in the NAPX register.
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂T₁₃ T₁₄ T₁₅ T₁₆T₁₇ T₁₈ T₁₉ T₂₀T₂₁ T₂₂ T₂₀₃ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂T₁₃ T₁₄ T₁₅ T₁₆T₁₇ T₁₈ T₁₉ T₂₀T₂₁ T₂₂ T₂₃
CTM/CFM
ROW2
..ROW0
COL4
..COL0
DQA8..0
DQB8..0
Power
State
RLXR
RLXC
RLXX
t_AS
ATTN
STBY
CTM/CFM
ROW2
..ROW0
COL4
..COL0
DQA8..0
DQB8..0
Power
State
ROP a0
COP a1
COCXPOOaCXPP1OOaaXPP11OaaCP11OaP1 a0
XOP a1 XOP a0
TFRM•t _CYCLE
t_SA
STBY
ATTN
ROP = non-broadcast ROWA
or ROWR/ATTN
a0 = {d0,b0,r0}
a1 = {d1,b1,c1}
No COL packets may be
placed in the three
indicated positions; i.e. at
(TFRM - {1,2,3})•t _CYCLE.
A COL packet to device d0
(or any other device) is okay
at
(TFRM)•t _CYCLE
or later.
A COL packet to another
device (d1!= d0) is okay at
(TFRM - 4)•t _CYCLE
or earlier.
Figure 46: STBY Entry (left) and STBY Exit (right)
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂T₁₃ T₁₄ T₁₅ T₁₆T₁₇ T₁₈ T₁₉ T₂₀T₂₁ T₂₂ T₂₀₃ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂T₁₃ T₁₄ T₁₅ T₁₆T₁₇ T₁₈ T₁₉ T₂₀T₂₁ T₂₂ T₂₃
CTM/CFM
ROW2
..ROW0
COL4
..COL0
DQA8..0
DQB8..0
Power
State
ROP a0
(NAPR)
COP a0
XOP a0
t_CD
re_qst_uri_ic_et_ted ROP a1
t_NPQ
re_qst_uri_ic_et_ted
COP a1
XOP a1
CTM/CFM
ROW2
..ROW0
COL4
..COL0
t_ASN
ATTN/STBY^a
DQA8..0
DQB8..0
NAP
Power
State
ROP a0
(PDNR)
COP a0
XOP a0
t_CD
r_qes_utr_iic_et_ted ROP a1
t_NPQ
r_qes_utr_iic_et_ted
COP a1
XOP a1
a0 = {d0,b0,r0,c0}
a1 = {d1,b1,r1,c1}
No ROW or COL packets
directed to device d0 may
overlap the restricted
interval. No broadcast ROW
packets may overlap the quiet
interval.
ROW or COL packets to a
device other than d0 may
overlap the restricted
interval.
t_ASP
ATTN/STBY^a
PDN
ROW or COL packets
directed to device d0 after the
restricted interval will be
ignored.
a _{The (eventual) NAP/PDN exit will be to the same ATTN/STBY state the RDRAM was in prior to NAP/PDN entry}
Figure 47: NAP Entry (left) and PDN Entry (right)
On the right side of Figure 49, an RDRAM exits PDN state
at the end of cycle T₃. This RDRAM may not re-enter PDN
or NAP state for an interval of t_PU0. The RDRAM enters
PDN state at the end of cycle T₁₃. This RDRAM may not re-
exit PDN state for an interval of t_PU1. The equations for
these two parameters depend upon a number of factors, and
are shown at the bottom of the figure. PDNX is the value in
the PDNX field in the PDNX register.
Page 40
Rev. 1.02 Jan. 2000