K4R271669A Datasheet, PDF (44/64 Pages) Samsung semiconductor – 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM

K4R271669A/K4R441869A
Direct RDRAM^™
Refresh
RDRAMs, like any other DRAM technology, use volatile
storage cells which must be periodically refreshed. This is
accomplished with the REFA command. Figure 50 shows an
example of this.
The REFA command in the transaction is typically a broad-
cast command (DR4T and DR4F are both set in the ROWR
packet), so that in all devices bank number Ba is activated
with row number REFR, where REFR is a control register in
the RDRAM. When the command is broadcast and ATTN is
set, the power state of the RDRAMs (ATTN or STBY) will
remain unchanged. The controller increments the bank
address Ba for the next REFA command. When Ba is equal
to its maximum value, the RDRAM automatically incre-
ments REFR for the next REFA command.
On average, these REFA commands are sent once every
t_REF/2^BBIT+RBIT (where BBIT are the number of bank
address bits and RBIT are the number of row address bits) so
that each row of each bank is refreshed once every t_REF
interval.
The REFA command is equivalent to an ACT command, in
terms of the way that it interacts with other packets (see
Table 10). In the example, an ACT command is sent after
t_RR to address b0, a different (non-adjacent) bank than the
REFA command.
A second ACT command can be sent after a time t_RC to
address c0, the same bank (or an adjacent bank) as the REFA
command.
Note that a broadcast REFP command is issued a time t_RAS
after the initial REFA command in order to precharge the
refreshed bank in all RDRAMs. After a bank is given a
REFA command, no other core operations (activate or
precharge) should be issued to it until it receives a REFP.
It is also possible to interleave refresh transactions (not
shown). In the figure, the ACT b0 command would be
replaced by a REFA b0 command. The b0 address would be
broadcast to all devices, and would be {Broadcast, Ba+2,
REFR}. Note that the bank address should skip by two to
avoid adjacent bank interference. A possible bank incre-
menting pattern would be: {13, 11, 9, 7, 5, 3, 1, 8, 10, 12, 14,
0, 2, 4, 6, 15, 29, 27, 25, 23, 21, 19, 17, 24, 26, 28, 30, 16,
18, 20, 22, 31}. Every time bank 31 is reached, the REFA
command would automatically increment the REFR register.
A second refresh mechanism is available for use in PDN and
NAP power states. This mechanism is called self-refresh
mode. When the PDN power state is entered, or when NAP
power state is entered with the NSR control register bit set,
then self-refresh is automatically started for the RDRAM.
Self-refresh uses an internal time base reference in the
RDRAM. This causes an activate and precharge to be
carried out once in every t_REF/2^BBIT+RBIT interval. The
REFB and REFR control registers are used to keep track of
the bank and row being refreshed.
Before a controller places an RDRAM into self-refresh
mode, it should perform REFA/REFP refreshes until the
bank address is equal to the maximum value. This ensures
that no rows are skipped. Likewise, when a controller returns
an RDRAM to REFA/REFP refresh, it should start with the
minimum bank address value (zero).
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂T₁₃ T₁₄ T₁₅ T₁₆T₁₇ T₁₈ T₁₉ T₂₀T₂₁ T₂₂ T₂₃ T₂₄T₂₅ T₂₆ T₂₇ T₂₈T₂₉ T₃₀ T₃₁ T₃₂T₃₃ T₃₄ T₃₅ T₃₆T₃₇ T₃₈ T₃₉ T₄₀T₄₁ T₄₂ T₄₃ T₄₄T₄₅ T₄₆ T₄₇
CTM/CFM
ROW2
REFA a0
..ROW0
COL4
..COL0
DQA8..0
DQB8..0
ACT b0
t_RR
t_RC
t_RAS
REFP a1
ACT c0
t_RP
t_REF/2^BBIT+RBIT
REFA d0
Transaction a: REFA a0 = {Broadcast,Ba,REFR}
Transaction b: xx b0 = {Db, /={Ba,Ba+1,Ba-1}, Rb}
Transaction c: xx
c0 = {Dc, ==Ba, Rc}
Transaction d: REFA d0 = {Broadcast,Ba+1,REFR}
a1 = {Broadcast,Ba}
BBIT = # bank address bits
RBIT = # row address bits
REFB = REFB3..REFB0
REFR = REFR8..REFR0
Figure 50: REFA/REFP Refresh Transaction Example
Page 42
Rev. 1.02 Jan. 2000