K4R271669A Datasheet, PDF(18/64 Page) Samsung semiconductor – 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM

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K4R271669A Datasheet, PDF (18/64 Pages) Samsung semiconductor – 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM

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K4R271669A/K4R441869A

Direct RDRAMâ¢

ROW-to-ROW Examples

Figure 10 shows examples of some of the ROW-to-ROW

packet spacings from Table 10. A complete sequence of acti-

vate and precharge commands is directed to a bank. The

RR8 and RR12 rules apply to this sequence. In addition to

satisfying the tRAS and tRP timing parameters, the separation

between ACT commands to the same bank must also satisfy

the tRC timing parameter (RR4).

When a bank is activated, it is necessary for adjacent banks

to remain precharged. As a result, the adjacent banks will

also satisfy parallel timing constraints; in the example, the

RR11 and RR3 rules are analogous to the RR12 and RR4

rules.

Same Device

Adjacent Bank

Same Bank

Adjacent Bank

Same Bank

RR7

RR3

RR4

RR11

RR12

a0 = {Da,Ba,Ra}

a1 = {Da,Ba+1}

b0 = {Da,Ba+1,Rb}

b0 = {Da,Ba,Rb}

b0 = {Da,Ba+1,Rb}

b0 = {Da,Ba,Rb}

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12T13 T14 T15 T16T17 T18 T19 T20T21 T22 T23 T24T25 T26 T27 T28T29 T30 T31 T32T33 T34 T35 T36T37 T38 T39 T40T41 T42 T43 T44T45 T46 T47

CTM/CFM

ROW2

..ROW0

ACT a0

PRER a1

ACT b0

COL4

..COL0

DQA8..0

DQB8..0

tRAS

tRC

tRP

Figure 10: Row Packet Example

Figure 11 shows examples of the ACT-to-ACT (RR1, RR2)

and ACT-to-PRER (RR5, RR6) command spacings from

Table 10. In general, the commands in ROW packets may be

spaced an interval tPACKET apart unless they are directed to

the same or adjacent banks or unless they are a similar

command type (both PRER or both ACT) directed to the

same device.

Different Device

Same Device

Different Device

Same Device

Any Bank

RR1

Non-adjacent Bank RR2

Any Bank

RR5

Non-adjacent Bank RR6

a0 = {Da,Ba,Ra}

b0 = {Db,Bb,Rb}

c0 = {Da,Bc,Rc}

b0 = {Db,Bb,Rb}

c0 = {Da,Bc,Rc}

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12T13 T14 T15 T16T17 T18 T19 T20T21 T22 T23 T24T25 T26 T27 T28T29 T30 T31 T32T33 T34 T35 T36T37 T38 T39 T40T41 T42 T43 T44T45 T46 T47

CTM/CFM

ROW2

..ROW0

COL4

..COL0

ACT a0

tPACKET

ACT b0

DQA8..0

DQB8..0

ACT a0

ACT c0

tRR

ACT a0 PRER b0

tPACKET

ACT a0 PRER c0

tPACKET

Figure 11: Row Packet Example

Page 16

Rev. 1.02 Jan. 2000

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