S3C24A0A Datasheet, PDF (505/519 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
CLOCK & POWER MANAGEMENT
Power Management
The power management block controls the system clocks by software for the reduction of power consumption in
S3C24A0A. These schemes are related to PLL, clock control logic(ARMCLK,HCLK,PCLK) and wake-up signal.
The Figure 33-5 depicts the clock distribution of S3C24A0A.
S3C24A0A has four power-down modes. The following section describes each power management mode.
ARM926-EJ
System
Configuration
Registers
MPLL_out
ARMclk
Fin
PLL
(Main & USB)
Clock Generation
(on/ off control)
MPEGclk
HCLK
PCLK
UPLLclk
UPLL_out
System
Configuration
Registers
VPOST
MPEG4ME
MPEG4DCTQ
VLX
MPEG4IF
LCD
CAMIF
VPOSTIF
USB Host
USB
IrDA
CAM
AC97
PWM TIMER
UART0
UART1
SPI
I2C
I2S
GPIO
USB Device
Memory Stick
SD
ADC
Key Pad
Figure 33-5. The Clock Distribution Block Diagram
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
33-9