S3C24A0A Datasheet, PDF (177/519 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

DMA
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
DMA OPERATION
The details of DMA operation can be explained using three-state FSM(finite state machine) as follows:
State-1.
State-2.
State-3.
As an initial state, it waits for the DMA request. If it comes, go to state-2. At this state, DMA ACK
and INT REQ are 0.
In this state, DMA ACK becomes 1 and the counter(CURR_TC) is loaded from DCON[19:0]
register. Note that DMA ACK becomes 1 and remains 1 until it is cleared later.
In this state, sub-FSM handling the atomic operation of DMA is initiated. The sub-FSM reads
the data from the source address and then writes it to destination address. In this operation, data
size and transfer size (single or burst) are considered. This operation is repeated until the counter
(CURR_TC) becomes 0 in the whole service mode, while performed only once in a single service
mode. The main FSM (this FSM) counts down the CURR_TC when the sub-FSM finishes each of
atomic operation. In addition, this main FSM asserts the INT REQ signal when CURR_TC
becomes 0 and the interrupt setting of DCON[28] register is set to 1. In addition, it clears DMA
ACK if one of the following conditions are met.
1. CURR_TC becomes 0 in the whole service mode
2. Atomic operation finishes in the single service mode.
Note that in the single service mode, these three states of main FSM are performed and then stops, and waits for
another DMA REQ. And if DMA REQ comes in all three states are repeated. Therefore, DMA ACK is asserted
and then de-asserted for each atomic transfer. In contrast, in the whole service mode, main FSM waits at state-3
until CURR_TC becomes 0. Therefore, DMA ACK is asserted during all the transfers and then de-asserted when
TC reaches 0.
However, INT REQ is asserted only if CURR_TC becomes 0 regardless of the service mode (single service mode
or whole service mode).
EXTERNAL DMA DREQ/DACK PROTOCOL
There are four types of external DMA request/acknowledge protocols. Each type defines how the signals like
DMA request and acknowledge are related to these protocols.
Basic DMA Timing
The DMA service means paired Reads and Writes cycles during DMA operation, which is one DMA operation.
The Figure 9-1 shows the basic Timing in the DMA operation of the S3C24A0A.
— The setup time and the delay time of XDREQ and XDACK are same in all the modes.
— If the completion of XDREQ meets its setup time, it is synchronized twice and then XDACK is asserted.
— After assertion of XDACK, DMA requests the bus and if it gets the bus it performs its operations. XDACK is
deasserted when DMA operation finishes.
9-2
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.