S3C24A0A Datasheet, PDF (181/519 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

DMA
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
DMA SPECIAL REGISTERS
There are seven control registers for each DMA channel. (Since there are four channels, the total number of
control registers is 28.) Four of them are to control the DMA transfer, and other three are to see the status of DMA
controller. The details of those registers are as follows.
DMA INITIAL SOURCE REGISTER (DISRC)
Register
DISRC0
DISRC1
DISRC2
DISRC3
Address
0x40400000
0x40500000
0x40600000
0x40700000
R/W
Description
R/W DMA0 initial source register
R/W DMA1 initial source register
R/W DMA2 initial source register
R/W DMA3 initial source register
Reset Value
0x00000000
0x00000000
0x00000000
0x00000000
DISRCn
S_ADDR
Bit
[30:0]
Description
These bits are the base address (start address) of source data
to transfer. This value will be loaded into CURR_SRC only if
the CURR_SRC is 0 and the DMA ACK is 1.
Initial State
0x00000000
DMA INITIAL SOURCE CONTROL REGISTER (DISRCC)
Register
DISRCC0
DISRCC1
DISRCC2
DISRCC3
Address
0x40400004
0x40500004
0x40600004
0x40700004
R/W
Description
R/W DMA0 initial source control register
R/W DMA1 initial source control register
R/W DMA2 initial source control register
R/W DMA3 initial source control register
Reset Value
0x00000000
0x00000000
0x00000000
0x00000000
DISRCn
LOC
INC
Bit
Description
Initial State
[1] Bit 1 is used to select the location of source.
0
0 = The source is in the system bus (AHB),
1 = The source is in the peripheral bus (APB)
[0] Bit 0 is used to select the address increment.
0
0 = Increment
1 = Fixed
If it is 0, the address is increased by its data size after each
transfer in burst and single transfer mode.
If it is 1, the address is not changed after the transfer (In the
burst mode, address is increased during the burst transfer, but
the address is recovered to its first value after the transfer).
9-6
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.