S3C24A0A Datasheet, PDF (447/519 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
LCD CONTROLLER
Individual Register Descriptions
LCD CONTROL 1 REGISTER
Register
LCDCON1
Address
0X4A000000
R/W
R/W
Description
LCD control 1 register
Reset Value
0x00000000
LCDCON1
BURSTLEN
Reserved
BDBCON
FDBCON
DIVEN
CLKVAL
CLKDIR
Reserved
PNRMODE
BPPMODEF
Bit
[29:28]
[27:22]
[21]
[20]
[19]
[18:13]
[12]
[11]
[10:9]
[8:6]
Description
DMA’s Burst Length selection:
00 = 16 word– burst
01 = 8 word– burst
10 = 4 word– burst
11 = Reserved
Reserved
Active Frame Select control for background image.
It will be adopted from next frame data.
0 = Buffer1
1 = Buffer2
Active Frame Select control for foreground image(OSD image).
It will be adopted from next frame data.
0 = Buffer1
1 = Buffer2
VCLK Divider( CLKVAL ) counter enable control bit
0 = Disable ( for Power saving)
1 = Enable
Determine the rates of VCLK and CLKVAL[5:0].
VCLK = HCLK / [(CLKVAL+1) x 2] (CLKVAL ≥ 0)
Select the clock source as direct or divide using CLKVAL
register.
0 = Direct clock
(frequency of VCLK = frequency of Clock source)
1 = Divided using CLKVAL
This bit should be ‘0’
Select the display mode.
00 = RGB Parallel mode (RGB)
01 = RGB Parallel mode (BGR)
10 = RGB Serial mode (R→G→B)
11 = RGB Serial mode (B→G→R)
Select the BPP (Bits Per Pixel) mode for foreground image
(OSD).
011 = 8 BPP (palettized)
100 = 8 BPP (non-palettized, R:3-G:3-B:2)
101 = 16 BPP (non-palettized, R:5-G:6-B:5)
110 = 16 BPP (non-palettized, R:5-G:5-B:5-I:1)
111 = unpacked 18 BPP (non-palettized)
Initial State
0
0
0
0
0
0
0
0
0
0
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
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