S3C24A0A Datasheet, PDF (224/519 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
IrDA CONTROLLER
TX
Enable
ACREG[7]
~ena
0
ena
1st Start
Flag
Transmit
1
str_end
Pay Load
Transmit
with stuff bit
abort by
underrun
2
pay_end
Append
Frame Data
with Error
CRC & Eflag
~abort
6
CRC
Transmit
with stuff bit
3
crc_end
Stop
sip
Flag
Transmit
4
stp_end & ena
2u
Pulse
transmit
5
pul_end & ena
stp_end & ~ena
pul_end & ~ena
Figure 12-5. Mir Modulation Process
Figure 12-5 shows MIR modulation state machine. This machine works very similarly with FIR modulation state
machine. The major difference is that the MIR data transmission needs bit stuffing. After the every 5 consecutive
ones, a zero data should be stuffed in MIR payload data. The state machine for this bit-stuffing is not presented
here.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
12-7