S3C24A0A Datasheet, PDF (135/519 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

INTERRUPT CONTROLLER
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
FUNCTIONAL DESCRIPTION
F-BIT AND I-BIT OF PSR (PROGRAM STATUS REGISTER)
If the F-bit of PSR (program status register in ARM926EJ CPU) is set to 1, the CPU does not accept the FIQ (fast
interrupt request) from the interrupt controller. If I-bit of PSR (program status register in ARM926EJ CPU) is set to
1, the CPU does not accept the IRQ (interrupt request) from the interrupt controller. So, to enable the interrupt
reception, the F-bit or I-bit of PSR has to be cleared to 0 and also the corresponding bit of INTMSK has to be set
to 0.
INTERRUPT MODE
ARM926EJ has 2 types of interrupt mode, FIQ or IRQ. All the interrupt sources determine the mode of interrupt to
be used at interrupt request.
INTERRUPT PENDING REGISTER
S3C24A0A has two interrupt pending resisters. The one is source pending register (SRCPND), the other is
interrupt pending register (INTPND). These pending registers indicate whether an interrupt request is pending or
not. When the interrupt sources request interrupt service the corresponding bits of SRCPND register are set to 1,
at the same time the only one bit of INTPND register is set to 1 automatically after arbitration process. If interrupts
are masked, the corresponding bits of SRCPND register are set to 1, but the bit of INTPND register is not
changed. Once the pending bit of INTPND register is set, then the interrupt service routine starts whenever the I-
flag or F-flag is cleared to 0. The SRCPND and INTPND registers can be read and written, so the service routine
must clear the pending condition by writing a 1 to the corresponding bit in SRCPND register first and then clear
the pending condition in INTPND registers same method.
INTERRUPT MASK REGISTER
This indicates that an interrupt has been disabled if the corresponding mask bit is 1. If an interrupt mask bit of
INTMSK is 0, the interrupt will be serviced normally. If the corresponding mask bit is 1 and the interrupt is
generated, the source pending bit will be set.
6-2
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.