S3C24A0A Datasheet, PDF (403/519 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
VLX
1 2 6 7 15 16 28 29
3 5 8 14 17 27 30 43
4 9 13 18 26 31 42 44
10 12 19 25 32 41 45 54
11 20 24 33 40 46 53 55
21 23 34 39 47 52 56 61
22 35 38 48 51 57 60 62
36 37 49 50 58 59 63 64
Figure 26-2. ZigZag Scanning Method
A three dimensional variable length coder is used to code transform coefficients. An EVENT is a combination of
three parameters
LAST 0: There are more nonzero coefficients in the block.
1: This is the last nonzero coefficient in the block.
RUN Number of zero coefficients preceding the current nonzero coefficient.
LEVEL Magnitude of the coefficient.
The most commonly occurring combinations of LAST, RUN, LEVEL are coded with variable length codes given
standard table. The remaining combinations, no matched case in table use three ESCAPE mode coding. First,
Level vaule change Level minus Lmax( Lmax is defined by RUN . Second, RUN value change RUN minus Rmax
(Rmax is defined by Level). Last, FLC, fixed length coding, are coded with a 22 bit word fixed length coding
consisting of ESCAPE (7-bit), LAST (1-bit ), RUN (6-bit ), LEVEL (8-bit), coding used.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
26-3