S3C24A0A Datasheet, PDF (497/519 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
CLOCK & POWER MANAGEMENT
33 CLOCK & POWER MANAGEMENT
OVERVIEW
The Clock & Power management unit consists of 3 parts; System Clock Control, USB Clock Control, and System
Power-management Control.
The System Clock Control logic in S3C24A0A can generate the required system clock signals, ARMCLK for CPU,
HCLK for the AHB-bus peripherals, and PCLK for the APB-bus peripherals. There are two PLLs in S3C24A0A.
One is for ARMCLK, HCLK, and PCLK, and the other is for the USB, IrDA and Camera Interface. The clock
control-logic can make slow clock without PLL and connect/disconnect the clock to each peripheral block by
software, which will reduce the power consumption.
In the power control logic, S3C24A0A has various power management schemes to keep optimal power
consumption for a given task. The power management in S3C24A0A consists of four modes: General Clock
Gating (NORMAL) mode, IDLE mode, STOP mode, and SLEEP mode.
General Clock Gating mode is used to control the On/Off of clocks for internal peripherals in S3C24A0A. The user
can optimize the power consumption of S3C24A0A using this General Clock Gating mode by supplying clocks for
peripherals that are necessary for a certain application. For example, if a timer is not needed, the user can
disconnect the clock to the timer to reduce power.
IDLE mode disconnects the ARMCLK only to CPU core while it supplies the clock to all peripherals. By using
IDLE mode, the power consumption due to CPU core can be reduced.
STOP mode freezes all clocks to the CPU as well as peripherals by disabling PLLs. The power consumption is
only due to the leakage current in S3C24A0A.
SLEEP mode is intended to disconnect the internal power. So, the power consumption due to CPU and the
internal logic except the wake-up logic will be zero in the SLEEP mode. In order to use the SLEEP mode two
independent power sources are needed. One of the two power sources supplies the power for the wake-up logic.
The other one supplies the other internal logic including CPU, and should be controlled in order to be turned
on/off. In SLEEP mode, the second power supply source for the CPU and internal logic will be turned off.
A detailed description of the power-saving modes such as the entering sequence to the specific power-down
mode or the wake-up sequence from a power-down mode is given in the following Power Management section.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
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