S3C24A0A Datasheet, PDF (504/519 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

CLOCK & POWER MANAGEMENT
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
MPEGCLK and CAMCLK frequency are determined by MPEGCLKdiv[3:0] and CAMCLKdiv[3:0] bits of CLKDIVN
control register.
MPEG or CAMCLKdiv[3:0]
0
1~15
MPEGCLK
HCLK
HCLK / ( 2 x MPEGCLKdiv )
CAMCLK
UPLL_clk
UPLL_clk / (CAMCLKdiv + 1 )
The MPEGCLK and the CAMCLK frequency are changed whenever the source clock frequency is changed.
UCLK (USB Clock) Control
USB host interface and USB device interface needs 48Mhz fixed-frequency clock. In the S3C24A0A, The USB
dedicated PLL (UPLL) generates 96Mhz and divided by two for USB block. UPLL will be turned off during STOP
and SLEEP mode automatically. Also, UPLL will be generated clock to USBCLK, IrDACLK, CAMCLK after exiting
STOP and SLEEP mode if USBon, IrDAclkOn and CAMclkOn bits are enabled in CLKCON register.
Condition
After reset
After configuring UPLL
UPLL is turned off by U_PLLoff bit in CLKSRC register
UPLL is turned on by U_PLLoff bit in CLKSRC register
UCLK state
UPLL output
During PLL lock time: Low
After PLL lock time: UPLL output
No clock
UPLL output
UPLL State
on
on
off
on
NOTE: UPLL_clk (UPLL output) is 98MHz. USBCLK is obtained by dividing by two of UPLL_clk, i.e. UPLL_clk/2.
33-8
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.