S3C24A0A Datasheet, PDF (399/519 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
MPEG-4 DCTQ
CONTROL REGISTER
Register
DCTQCTRL
Address
0x4900_0034
R/W
Description
RW Control register
Reset Value
0x00000000
DCTQCTRL
Reserved
Coeff_not_write
With_VLC
DCT_only
IDCT_only
SWRST
OPUNIT
DCTQBSY
DCTQST
Reserved
ISH263
Reserved
ISENC
Reserved
FRST
Bit
[31:30]
[29]
[28]
[27]
[26]
[25]
[24:8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Description
Reserved
Coefficients write operation to memory can be skipped with
VLC IP ‘On’ state. In this case, DCTQ engine write the
coefficient to the internal memory of VLC directly.
DCTQ operates by MB-unit with watching VLC operation
(BUSY).
In decoder mode, this bit must be zero. If only DCTQ is
operating, this bit should be zero.
Quantization skip for JPEG mode
De-quantization skip for JPEG mode
This bit indicates the software reset of MPEG-4 DCTQ.
These bits controls the number of DCTQ operations by
macroblock unit. If these bits are 14’d99 in QCIF size, DCTQ
operates during one frame without command.
This bit indicates the busy state of DCTQ.
1 = DCTQ is operating.
0 = DCTQ is not operating.
This bit indicates the start of DCTQ operation. This bit is auto-
cleared.
Reserved
This bit indicates that the format of current DCTQ operation is
H.263 or not.
1 = H.263 (without padding)
0 = MPEG-4 (with padding)
Reserved
This bit indicates that the current DCTQ operation is encoding
or not.
1 = Encoding
0 = Decoding
Reserved
This bit indicates the frame start signal, which is active only
first OPUNIT.
1 = Frame start
0 = Normal
Initial State
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved SFR 0x49000038
Reserved SFR 0x4900003c
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
25-13