S3C24A0A Datasheet, PDF (137/519 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

INTERRUPT CONTROLLER
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
INTERRUPT PRIORITY GENERATING BLOCK
The priority logic for 32 interrupt requests is composed of seven rotation based arbiters: six first-level arbiters and
one second-level arbiter as shown in the following Figure.
ARBITER6
ARBITER0
ARBITER1
ARBITER2
ARBITER3
ARBITER4
ARBITER5
REQ1/EINT0_2
REQ2/EINT3_6
REQ3/EINT7_10
REQ4/EINT11_14
REQ1/EINT15_18
REQ2/INT_TIC
REQ3/DCTQ
REQ4/INT_MC
REQ5/INT_ME
REQ6/INT_Keypad
REQ1/INT_Timer0
REQ2/INT_Timer1
REQ3/INT_Timer2
REQ4/INT_Timer3,4
REQ5/INT_LCD_POST
REQ6/INT_CAMIF_CODEC
REQ1/INT_WDT_BATFLT
REQ2/INT_UART0
REQ3/INT_CAMIF_PREVIEW
REQ4/INT_MODEM
REQ5/INT_DMA
REQ6/INT_SDI
REQ1/INT_SPI0
REQ2/INT_UART1
REQ3/INT_AC97_NFLASH
REQ4/INT_USBD
REQ5/INT_USBH
REQ6/INT_IIC
REQ1/INT_IrDA_MSTICK
REQ2/INT_VLC_SPI1
REQ3/INT_RTC
REQ4/INT_ADC_PENUP_PENDN
Figure 6-1. Priority Generating Block
6-4
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.