S3C24A0A Datasheet, PDF (212/519 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
UART
UART TX/RX STATUS REGISTER
There are two UART Tx/Rx status registers, UTRSTAT0 and UTRSTAT1 in the UART block.
Register
UTRSTAT0
UTRSTAT1
Address
0x44400010
0x44404010
R/W
Description
R UART channel 0 Tx/Rx status register
R UART channel 1 Tx/Rx status register
Reset Value
0x6
0x6
UTRSTATn
Transmitter empty
Transmit buffer empty
Receive buffer data
ready
Bit
Description
Initial State
[2] This bit is automatically set to 1 when the transmit buffer
1
register has no valid data to transmit and the transmit
shift register is empty.
0 = Not empty
1 = Transmitter(transmit buffer & shifter register) empty
[1] This bit is automatically set to 1 when transmit buffer
1
register is empty.
0 =The buffer register is not empty
1 = Empty
(In Non-FIFO mode, Interrupt or DMA is requested.
In FIFO mode, Interrupt or DMA is requested, when
Tx FIFO Trigger Level is set to 00(Empty))
If the UART uses the FIFO, users should check Tx FIFO
Count bits and Tx FIFO Full bit in the UFSTAT register
instead of this bit.
[0] This bit is automatically set to 1 whenever receive buffer
0
register contains valid data, received over the RXDn port.
0 = Empty
1 = The buffer register has a received data
(In Non-FIFO mode, Interrupt or DMA is requested)
If the UART uses the FIFO, users should check Rx FIFO
Count bits and Rx FIFO Full bit in the UFSTAT register
instead of this bit.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
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