S3C24A0A Datasheet, PDF (173/519 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

WATCHDOG TIMER
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
WATCHDOG TIMER OPERATION
The functional block diagram of the watchdog timer is shown in Figure 8-1. The watchdog timer uses PCLK as its
only source clock. To generate the corresponding watchdog timer clock, the PCLK frequency is prescaled first,
and the resulting frequency is divided again.
PCLK
8-bit Prescaler
1/16
1/32
1/64
1/128
MUX
WTDAT
WTCNT
(Down Counter)
Interrupt
Reset Signal Generator
RESET
WTCON[15:8]
WTCON[4:3]
WTCON[2]
WTCON[0]
Figure 8-1. Watchdog Timer Block Diagram
The prescaler value and the frequency division factor are specified in the watchdog timer control register,
WTCON. The valid prescaler values range from 0 to 2⁸-1. The frequency division factor can be selected as 16,
32, 64, or 128.
Use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock
cycle:
t_watchdog = 1/( PCLK / (Prescaler value + 1) / Division_factor )
WTDAT & WTCNT
When the watchdog timer is enabled first, the value of WTDAT (watchdog timer data register) cannot be
automatically reloaded into the WTCNT (timer counter). For this reason, an initial value must be written to the
watchdog timer count register, WTCNT, before the watchdog timer starts.
CONSIDERATION OF DEBUGGING ENVIRONMENT
When S3C24A0A is in debug mode using Embedded ICE, the watchdog timer must not operate.
The watchdog timer can determine whether or not the current mode is the debug mode from the CPU core signal
(DBGACK signal). Once the DBGACK signal is asserted, the reset output of the watchdog timer is not activated
when the watchdog timer is expired.
8-2
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.