S3C24A0A Datasheet, PDF (228/519 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
IrDA CONTROLLER
IrDA MODE DEFINITION REGISTER(IrDA_MDR)
Register
IrDA_MDR
Address
0x41800004
R/W
Description
R/W IrDA mode definition register
Reset Value
0x00
IrDA _MDR
Reserved
SIP Select
Temic select
Mode select
Bit
Description
[7:5] Reserved
[4] SIP select method. If this bit is set to ‘1’ and the IrDA_CNT[3]
is set to ‘1’, the SIP pulse is appended at the end of FIR/MIR
TX frame. Likewise, when this bit is set to a ‘0’, SIP is
generated at the end of the every FIR/MIR frames. If
IrDA_CNT[3] is set to ‘0’, setting this bit to ‘1’ doesn’t help to
generate SIP. Along with IrDA_CNT[3] bit, the way of SIP
generation can be controlled.
[3] Bit 3 is Temic transceiver select bit. When bit 3 is clear to “0”,
core automatically selects in Temic transceiver mode.
[2:0] Bit 2, bit 1 and bit 0 select the mode of operation as
100 = FIR Mode
010 = MIR Mode
Initial State
0
0
0
0
IrDA INTERRUPT / DMA CONFIGURATION REGISTER (IrDA_CNF)
Register
IrDA_CNF
Address
0x41800008
R/W
Description
R/W IrDA interrupt / DMA configuration register
IrDA _CNF
Reserved
DMA Enable
DMA Mode
Reserved
Interrupt Enable
Bit
Description
[7:4] Reserved
[3] 1 = DMA enable
[2] 0 = Tx DMA
1 = Rx DMA
[1] Reserved
[0] The bit 0 enables Interrupt output signal.
Reset Value
0x00
Initial State
–
0
0
–
0
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
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