S3C24A0A Datasheet, PDF (25/519 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

List of Figures (Continued)
Figure
Number
14-1
14-2
15-1
15-2
16-1
16-2
16-3
16-4
16-5
16-6
16-7
16-8
17-1
18-1
19-1
19-2
19-3
19-4
21-1
21-2
21-3
21-4
21-5
21-6
21-7
21-8
21-9
21-10
21-11
21-12
21-13
Title
Page
Number
IIS-Bus Block Diagram ...........................................................................................................14-1
IIS-Bus and MSB(Left)-justified Data Interface Formats ........................................................14-4
SPI Block Diagram ..................................................................................................................15-2
SPI Transfer Format ................................................................................................................15-4
AC97 Block Diagram ...............................................................................................................16-2
Internal Data Path....................................................................................................................16-3
AC97 Operation Flow Chart ....................................................................................................16-4
Bi-directional AC-link Frame with Slot Assignments ...............................................................16-5
AC-link Output Frame..............................................................................................................16-6
AC-link Input Frame.................................................................................................................16-6
AC97 Powerdown Timing ........................................................................................................16-7
AC97 Power down/Power up Flow..........................................................................................16-8
USB Host Controller Block Diagram........................................................................................17-1
USB Device Block Diagram.....................................................................................................18-2
Modem Interface Overview......................................................................................................19-1
Modem Interface Address Mapping ........................................................................................19-3
Modem Interface Write Timing Diagram..................................................................................19-4
Modem Interface Read Timing Diagram .................................................................................19-5
Camera Interface Overview.....................................................................................................21-1
ITU-R BT 601 Input Timing Diagram.......................................................................................21-3
ITU-R BT 656 Input Timing Diagram.......................................................................................21-3
IO Connection Guide ...............................................................................................................21-5
Two DMA Ports........................................................................................................................21-6
Clock Generation.....................................................................................................................21-7
Ping-pong Memory Hierarchy..................................................................................................21-8
Memory Storing Style ..............................................................................................................21-9
Timing Diagram for Register Setting .......................................................................................21-10
Timing Diagram for Last IRQ...................................................................................................21-11
Window Offset Scheme ...........................................................................................................21-13
Image Mirror and Rotation.......................................................................................................21-18
Scaling scheme .......................................................................................................................21-20
S3C24A0A MICROPROCESSOR
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