S3C24A0A Datasheet, PDF (198/519 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
UART
11 UART
OVERVIEW
The S3C24A0A UART (Universal Asynchronous Receiver and Transmitter) unit provides two independent
asynchronous serial I/O (SIO) ports, each of which can operate in interrupt-based or DMA-based mode. In other
words, UART can generate an interrupt or DMA request to transfer data between CPU and UART. It can support
bit rates of up to 115.2K bps, when UART use system clock. If external device provides UART with UCLK, then
UART can operates at more higher speed. Each UART channel contains two 64-byte FIFOs for receiver and
transmitter.
The S3C24A0A UART includes programmable baud-rates, infrared (IR) transmit/receive, one or two stop bit
insertion, 5-bit, 6-bit, 7-bit or 8-bit data width and parity checking.
Each UART contains a baud-rate generator, transmitter, receiver and control unit, as shown in Figure11-1. The
baud-rate generator can be clocked by PCLK. The transmitter and the receiver contain 64-byte FIFOs and data
shifters. Data, which is to be transmitted, is written to FIFO and then copied to the transmit shifter. It is then shifted
out by the transmit data pin (TxDn). The received data is shifted from the receive data pin (RxDn), and then
copied to FIFO from the shifter.
FEATURES
— RxD0, TxD0, RxD1, TxD1 with DMA-based or interrupt-based operation
— UART Ch 0, 1 with IrDA 1.0 & 64-byte FIFO
— UART Ch 0, 1 with nRTS0, nCTS0, nRTS1, nCTS1
— Supports handshake transmit / receive
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
11-1