S3C24A0A Datasheet, PDF (449/519 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
LCD CONTROL 2 REGISTER
Register
LCDCON2
Address
0X4A000004
R/W
R/W
Description
LCD control 2 register
LCDCON2
LINECNT
(read only)
VSTATUS
HSTATUS
PALFRM
Reserved
IVCLK
IHSYNC
IVSYNC
Reserved
IVDEN
BITSWP
BYTSWP
HAWSWP
Bit
[25:15]
[14:13]
[12:11]
[10:9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Description
Provide the status of the line counter (read only)
Up count from 0 to LINEVAL
Vertical Status (read only).
00 = VSYNC
10 = ACTIVE
01 = BACK Porch
11 = FRONT Porch
Horizontal Status (read only).
00 = HSYNC
01 = BACK Porch
10 = ACTIVE
11 = FRONT Porch
This bit determines the size of the palette data format
00 = Reserved
01 = 18-bit ( 6:6:6)
10 = 16-bit (5:6:5)
11 = 16-bit ( 5:5:5:1)
This bit must be “0”.
This bit controls the polarity of the VCLK active edge.
0 = The video data is fetched at VCLK falling edge
1 = The video data is fetched at VCLK rising edge
This bit indicates the HSYNC pulse polarity.
0 = Normal
1 = Inverted
This bit indicates the VSYNC pulse polarity.
0 = Normal
1 = Inverted
Reserved
This bit indicates the VDEN signal polarity.
0 = Normal
1 = Inverted
Bit swap control bit.
0 = Swap Disable
1 = Swap Enable
Byte swap control bit.
0 = Swap Disable
1 = Swap Enable
Half-Word swap control bit.
0 = Swap Disable
1 = Swap Enable
LCD CONTROLLER
Reset Value
0x00000000
Initial state
0
0
0
0
0
0
0
0
0
0
0
0
0
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
28-19