S3C24A0A Datasheet, PDF (199/519 Pages) Samsung semiconductor – 32-BIT RISC MICROPROCESSOR

UART
BLOCK DIAGRAM
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
Peripheral BUS
Transmitter
Transmit Buffer
Register(64 Byte)
Transmit Shifter
Transmit FIFO Register
(FIFO mode)
Transmit Holding Register
(Non-FIFO mode)
TXDn
Control
Unit
Buad-rate
Generator
Receiver
Receive Shifter
Clock Source
RXDn
Receive Buffer
Register(64 Byte)
Receive Holding Register
(Non-FIFO mode only)
Receive FIFO Register
(FIFO mode)
In FIFO mode, all 64 Byte of Buffer register are used as FIFO register.
In non-FIFO mode, only 1 Byte of Buffer register is used as Holding register.
Figure 11-1. UART Block Diagram (with FIFO)
11-2
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.