RX21A_15 Datasheet, PDF (96/132 Pages) Renesas Technology Corp – Renesas MCUs

RX21A Group
5. Electrical Characteristics
Table 5.35 Timing of On-Chip Peripheral Modules (6)
Conditions: VCC = AVCC0 = AVCCA = 2.7 to 3.6 V, VSS = AVSS0 = AVSSA = VREFL = VREFL0 = VREFDSL = 0 V,
T_a = –40 to +105°C
Item
Simple IIC
(Standard mode)
Simple IIC
(Fast mode)
SDA input rise time
SDA input fall time
SDA input spike pulse removal time
Data input setup time
Data input hold time
SCL, SDA capacitive load
SDA input rise time
SDA input fall time
SDA input spike pulse removal time
Data input setup time
Data input hold time
SCL, SDA capacitive load
Symbol
t_Sr
t_Sf
t_SP
t_SDAS
t_SDAH
C_b
t_Sr
t_Sf
t_SP
t_SDAS
t_SDAH
C_b
Min.*¹
—
—
0
250
0
—
20 + 0.1C_b
20 + 0.1C_b
0
100
0
—
Max.
1000
300
4 × t_pcyc*²
—
—
400
300
300
4 × t_pcyc*²
—
—
400
Unit
Test
Conditions
ns Figure
ns
5.54
ns
ns
ns
pF
ns ^Figure
ns
5.54
ns
ns
ns
pF
Note: • t_Pcyc: PCLK cycle
Note 1. C_b indicates the total capacity of the bus line.
Note 2. This applies when the SMR.CKS[1:0] bits = 00b and the SNFR.NFCS[2:0] bits = 010b while the SNFR.NFE bit = 1 and the digital
filter is enabled.
R01DS0129EJ0110 Rev.1.10
Aug 28, 2014
Page 96 of 132