RX21A_15 Datasheet, PDF (93/132 Pages) Renesas Technology Corp – Renesas MCUs

RX21A Group
5. Electrical Characteristics
Table 5.32 Timing of On-Chip Peripheral Modules (3)
Conditions: VCC = AVCC0 = AVCCA = 1.8 to 3.6 V, VSS = AVSS0 = AVSSA = VREFL = VREFL0 = VREFDSL = 0 V,
T_a = –40 to +105°C
When high-drive output is selected by the drive capacity register
Item
Symbol
Min.
Max.
Unit*¹ Test Conditions
RSPI RSPCK clock cycle Master
t_SPcyc
2
2.7 V ≤ VCC ≤ 3.6 V
4096
t_Pcyc C = 30 pF
Figure 5.49
Master
1.8 V ≤ VCC < 2.7 V
4
4096
Slave
8
4096
RSPCK clock high
pulse width
Master
Slave
RSPCK clock low
pulse width
Master
Slave
RSPCK clock rise/fall Output
time
Input
t_SPCKWH
(t_SPcyc – t_SPCKr –
—
ns
t_SPCKf)/2 – 3
(t_SPcyc – t_SPCKr –
—
t_SPCKf)/2
t_SPCKWL
(t_SPcyc – t_SPCKr –
—
ns
t_SPCKf)/2 – 3
(t_SPcyc – t_SPCKr –
—
t_SPCKf)/2
t_SPCKr, t_SPCKf
—
10
ns
—
1
μs
Data input setup time Master
t_SU
4
2.7 V ≤ VCC ≤ 3.6 V
Master
16
1.8 V ≤ VCC < 2.7 V
—
ns C = 30 pF
Figure 5.50 to
—
Figure 5.53
Data input hold time
SSL setup time
SSL hold time
Data output delay
time
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
2.7 V ≤ VCC ≤ 3.6 V
t_H
t_LEAD
t_LAG
t_OD
20 – t_Pcyc
t_Pcyc
20 + 2 × t_Pcyc
1
4
1
4
—
—
—
—
—
8
—
8
—
10
3 × t_Pcyc + 55
ns
t_SPcyc
t_Pcyc
t_SPcyc
t_Pcyc
ns
Slave
1.8 V ≤ VCC < 2.7 V
—
3 × t_Pcyc + 72
Data output hold time Master
Slave
t_OH
0
0
—
ns
—
Successive
transmission delay
time
Master
Slave
MOSI and MISO rise/ Output
fall time
Input
t_TD
t_Dr, t_Df
t_SPcyc + 2 × t_Pcyc 8 × t_SPcyc + 2 ×
ns
t_Pcyc
4 × t_Pcyc
—
—
10
ns
—
1
μs
SSL rise/fall time
Output
Input
t_SSLr, t_SSLf
—
—
20
ns
1
μs
Slave access time
t_SA
—
Slave output release 2.7 V ≤ VCC ≤ 3.6 V
t_REL
—
time
1.8 V ≤ VCC < 2.7 V
—
5
t_Pcyc C = 30 pF
4
t_Pcyc
Figure 5.52 and
Figure 5.53
5
Note 1. t_Pcyc: PCLK cycle
R01DS0129EJ0110 Rev.1.10
Aug 28, 2014
Page 93 of 132