RX21A_15 Datasheet, PDF (49/132 Pages) Renesas Technology Corp – Renesas MCUs

RX21A Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (18 / 24)
Address
0008 B444h
0008 B448h
0008 B450h
0008 B451h
0008 B452h
0008 B453h
0008 B454h
0008 B458h
0008 B460h
0008 B461h
0008 B462h
0008 B463h
0008 B464h
0008 B468h
0008 B470h
0008 B471h
0008 B472h
0008 B473h
0008 B474h
0008 B478h
0008 C000h
0008 C001h
0008 C002h
0008 C003h
0008 C004h
0008 C005h
0008 C00Ah
0008 C00Bh
0008 C00Ch
0008 C00Eh
0008 C011h
0008 C012h
0008 C020h
0008 C021h
0008 C022h
0008 C023h
0008 C024h
0008 C025h
0008 C02Ah
0008 C02Bh
0008 C02Ch
0008 C02Eh
0008 C031h
0008 C032h
0008 C040h
Module
Symbol
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
DSAD
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORTA
PORTB
PORTC
PORTE
PORTH
PORTJ
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORTA
PORTB
PORTC
PORTE
PORTH
PORTJ
PORT0
Register Name
∆Σ A/D data register 3
∆Σ A/D input select register 3
∆Σ A/D control register 4
∆Σ A/D control/status register 4
∆Σ A/D gain select register 4
∆Σ A/D overwrite flag register 4
∆Σ A/D data register 4
∆Σ A/D input select register 4
∆Σ A/D control register 5
∆Σ A/D control/status register 5
∆Σ A/D gain select register 5
∆Σ A/D overwrite flag register 5
∆Σ A/D data register 5
∆Σ A/D input select register 5
∆Σ A/D control register 6
∆Σ A/D control/status register 6
∆Σ A/D gain select register 6
∆Σ A/D overwrite flag register 6
∆Σ A/D data register 6
∆Σ A/D input select register 6
Port direction register
Port direction register
Port direction register
Port direction register
Port direction register
Port direction register
Port direction register
Port direction register
Port direction register
Port direction register
Port direction register
Port direction register
Port output data register
Port output data register
Port output data register
Port output data register
Port output data register
Port output data register
Port output data register
Port output data register
Port output data register
Port output data register
Port output data register
Port output data register
Port input data register
Register
Symbol
DSADDR3
DSADISR3
DSADCR4
DSADCSR4
DSADGSR4
DSADFR4
DSADDR4
DSADISR4
DSADCR5
DSADCSR5
DSADGSR5
DSADFR5
DSADDR5
DSADISR5
DSADCR6
DSADCSR6
DSADGSR6
DSADFR6
DSADDR6
DSADISR6
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PDR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PODR
PIDR
0008 C041h PORT1 Port input data register
PIDR
Number of Access Cycles
Number Access ICLK 
of Bits Size
PCLK
ICLK <
PCLK
32
32
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
32
32
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
32
32
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
32
32
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
2, 3 PCLKB
2 ICLK
8
8
3 or 4 PCLKB cycles 3 ICLK cycles when
when reading,
reading,
2 or 3 PCLKB cycles 2 ICLK cycles when
when writing
writing
8
8
3 or 4 PCLKB cycles 3 ICLK cycles when
when reading,
reading,
2 or 3 PCLKB cycles 2 ICLK cycles when
when writing
writing
R01DS0129EJ0110 Rev.1.10
Aug 28, 2014
Page 49 of 132