RX21A_15 Datasheet, PDF (82/132 Pages) Renesas Technology Corp – Renesas MCUs

RX21A Group
5.4 Clock Timing
5. Electrical Characteristics
Table 5.26 Clock Timing
Conditions: VCC = AVCC0 = AVCCA = 1.8 to 3.6 V, VSS = AVSS0 = AVSSA = VREFL = VREFL0 = VREFDSL = 0 V,
T_a = –40 to +105°C
Item
Symbol
Min.
Typ.
Max.
Unit
Test
Conditions
EXTAL external clock input cycle time
t_EXcyc
50
—
—
ns Figure 5.25
EXTAL external clock input high pulse width
t_EXH
20
—
—
ns
EXTAL external clock input low pulse width
t_EXL
20
—
—
ns
EXTAL external clock rising time
t_EXr
—
—
5
ns
EXTAL external clock falling time
t_EXf
—
—
5
ns
EXTAL external clock input wait time*¹
t_EXWT
1
—
—
ms
Main clock oscillator oscillation frequency*²
f_MAIN
1
—
20 MHz
Main clock oscillation stabilization time (crystal)*²
t_MAINOSC
—
3
—
ms Figure 5.26
Main clock oscillation stabilization time (ceramic resonator)*²
t_MAINOSC
—
50
µs
Main clock oscillation stabilization wait time (crystal)*²
t_MAINOSCWT
—
6
—
ms
Main clock oscillation stabilization wait time (ceramic resonator)*² t_MAINOSCWT —
100
µs
LOCO, IWDTCLK clock cycle time
t_cyc
7.27
8
8.89 µs
LOCO, IWDTCLK clock oscillation frequency
f_LOCO
112.5 125 137.5 kHz
LOCO, IWDTCLK clock oscillation stabilization wait time
t_LOCOWT
—
—
20
µs Figure 5.27
HOCO clock oscillation frequency
f_HOCO
31.680 32 32.320 MHz Ta = 0 to
36.495 36.864 37.233
50°C
39.600 40 40.400
49.500 50 50.500
31.520 32 32.480
36.311 36.864 37.417
Ta = -40 to
105°C
39.400 40 40.600
49.250 50 50.750
HOCO clock oscillation stabilization time 1
t_HOCO1
—
—
300
µs Figure 5.28
HOCO clock oscillation stabilization time 2
t_HOCO2
—
—
175
µs Figure 5.29
HOCO clock oscillation stabilization wait time
t_HOCOWT
—
—
350
µs Figure 5.29
HOCO clock power supply stabilization time
t_HOCOP
—
—
350
µs Figure 5.30
PLL input frequency
f_PLLIN
4
—
12.5 MHz
PLL circuit oscillation frequency
f_PLL
50
—
100 MHz
PLL clock oscillation stabilization time
PLL operation started
t_PLL1
—
—
500
µs Figure 5.31
after main clock
PLL clock oscillation stabilization wait time _{oscillation has settled}
t_PLLWT1
1.5
—
—
ms
PLL clock oscillation stabilization time*⁴
PLL clock oscillation stabilization wait
time*⁴
PLL operation started
before main clock
oscillation has settled
t_PLL2
t_PLLWT2
—
3.5*³
—
ms Figure 5.32
—
7
—
ms
PLL clock power supply stabilization time
t_PLLPW
—
—
30
µs Figure 5.33
Sub-clock oscillator oscillation frequency
f_SUB
— 32.768 —
kHz
Sub-clock oscillation stabilization time*⁵
t_SUBOSC
2
—
—
s Figure 5.34
Sub-clock oscillation stabilization wait time*⁵
t_SUBOSCWT
4
—
—
s
Note 1. The time interval from the time P36 and P37 are configured for input and the main clock oscillator stopping bit
(MOSCCR.MOSTP) is set to 0 (operating) until the clock becomes available.
R01DS0129EJ0110 Rev.1.10
Aug 28, 2014
Page 82 of 132