RX21A_15 Datasheet, PDF (61/132 Pages) Renesas Technology Corp – Renesas MCUs

RX21A Group
5. Electrical Characteristics
Item
Supply Low-speed
current*¹ operating mode
1
Normal operating No peripheral
mode
operation*⁶
Sleep mode
All peripheral
operation:
Normal*⁷
All peripheral
operation:
Max.*⁸
No peripheral
operation
All peripheral
operation:
Normal
All-module clock stop mode
Low-speed
operating mode
2
Normal operating No peripheral
mode
operation*⁹
All peripheral
operation:
Normal*¹⁰
All peripheral
operation:
Max.*¹¹
Sleep mode
No peripheral
operation
All peripheral
operation:
Normal
All-module clock stop mode
ICLK = 8 MHz
ICLK = 4 MHz
ICLK = 8 MHz
ICLK = 4 MHz
ICLK = 8 MHz
ICLK = 8 MHz
ICLK = 4 MHz
ICLK = 8 MHz
ICLK = 4 MHz
ICLK = 8 MHz
ICLK = 4 MHz
ICLK = 32 kHz
ICLK = 32 kHz
ICLK = 32 kHz
ICLK = 32 kHz
ICLK = 32 kHz
ICLK = 32 kHz
Symbol
Typ.
Max.
Unit
Test
Conditions
I_CC
1.9 — mA
1.2 —
2.5 —
1.7 —
—
12
1.3 —
0.9 —
1.9 —
1.3 —
1.1 —
0.9 —
0.027 —
0.030 —
— 1.0
0.022 —
0.025 —
0.022 —
Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when internal pull-up MOSs
are in the off state.
Note 2. This is the increase if data is programmed to or erasing from the ROM or E2 DataFlash during program execution.
Note 3. Clock supply to the peripheral functions is stopped. This does not include BGO operation. The clock source is HOCO. FCLK and
PCLK are set to divided by 64.
Note 4. Clocks are supplied to the peripheral functions. This does not include BGO operation. The clock source is HOCO. FCLK and
PCLK are set to divided by 64.
Note 5. Clocks are supplied to the peripheral functions. This does not include BGO operation. The clock source is PLL. FCLK and PCLK
are ICLK divided by 1.
Note 6. Clock supply to the peripheral functions is stopped. This does not include BGO operation. The clock source is the main
oscillation circuit. FCLK and PCLK are set to divided by 64.
Note 7. Clocks are supplied to the peripheral functions. This does not include BGO operation. The clock source is the main oscillation
circuit. FCLK and PCLK are set to divided by 64.
Note 8. Clocks are supplied to the peripheral functions. This does not include BGO operation. The clock source is HOCO. FCLK and
PCLK are ICLK divided by 1.
Note 9. Clock supply to the peripheral functions is stopped. This does not include BGO operation. The clock source is the sub oscillation
circuit. FCLK and PCLK are set to divided by 64.
Note 10. Clocks are supplied to the peripheral functions. This does not include BGO operation. The clock source is the sub oscillation
circuit. FCLK and PCLK are set to divided by 64.
Note 11. Clocks are supplied to the peripheral functions. This does not include BGO operation. The clock source is the main oscillation
circuit. FCLK and PCLK are ICLK divided by 1.
R01DS0129EJ0110 Rev.1.10
Aug 28, 2014
Page 61 of 132