RX21A_15 Datasheet, PDF (116/132 Pages) Renesas Technology Corp – Renesas MCUs

RX21A Group
5. Electrical Characteristics
Table 5.45 Power-on Reset Circuit and Voltage Detection Circuit Characteristics (2)
Conditions: VCC = AVCC0 = AVCCA, VSS = AVSS0 = AVSSA = VREFL = VREFL0 = VREFDSL = 0 V, T_a = –40 to +105°C
Item
Symbol
Min.
Typ.
Max. Unit Test Conditions
Voltage detection Voltage detection circuit (LVD2)*¹
level
Internal reset time Power-on reset time
Voltage monitoring 0 reset time
Voltage monitoring 1 reset time
Voltage monitoring 2 reset time
Minimum VCC down time*²
Response delay time
LVD operation stabilization time (after LVD is enabled)
V_{det2_7}
V_{det2_8}
V_{det2_9}
V_{det2_A}
V_{det2_B}
V_{det2_C}
V_{det2_D}
V_{det2_E}
V_{det2_F}
V_CMPA2
t_POR
t_LVD0
t_LVD1
t_LVD2
t_VOFF
t_det
Td_(E-A)
2.95
2.85
2.70
2.55
2.40
2.25
2.10
1.95
1.80
1.18
—
—
—
—
200
—
—
3.10
2.95
2.80
2.65
2.50
2.35
2.20
2.05
1.90
1.33
9
9
1.4
1.4
—
—
—
3.25
V Figure 5.68
3.05
At falling edge
2.90
VCC
2.75
2.60
2.45
2.30
2.15
2.00
1.48
EXVCCINP2 = 1
—
ms Figure 5.65
—
Figure 5.66
—
Figure 5.67
—
Figure 5.68
—
µs Figure 5.65
200
µs Figure 5.65
15
µs Figure 5.67 and
Figure 5.68
Power-on reset enable time
t_W(POR)
1
—
—
ms Figure 5.65
VCC = 0.9 V or
lower
Hysteresis width (LVD1 and LVD2)
V _LVH
—
100
—
mV When selection is
from among
VdetX_7.
—
50
—
When selection is
from among
VdetX_8 to F.
Note: • These characteristics apply when noise is not superimposed on the power supply.
Note 1. # in the symbol Vdet2_# denotes the value of the LVDLVLR.LVD2LVL[3:0] bits.
Note 2. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels V_POR, V_det0,
V_det1, and V_det2 for the POR/ LVD.
VCC
V_POR
t_VOFF
Internal reset signal
(active-low)
Figure 5.64 Voltage Detection Reset Timing
R01DS0129EJ0110 Rev.1.10
Aug 28, 2014
t_det
t_det t_POR
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